Fung Fung Lee - Milpitas CA, US Chukwuweta Chukwudebe - Milpitas CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50 G06F 9/45
US Classification:
716 1, 716 8
Abstract:
Method and apparatus are described for generating a block diagram of an electronic circuit design. In one embodiment, each instance of a multi-master bus, a bus master of a multi-master bus, a bus slave of a multi-master bus, a memory, a co-processor and an input/output port is are identified. Instances of input/output ports are placed about a perimeter of a first area of the diagram. Each instance of a multi-master bus is placed in a bus area within the first area and each bus master is placed in a master area. The bus slaves of a bus are collected in a group, and the group is placed as a single block in a slave area within the first area. The group of bus slave slaves is aligned with a bus master. A diagrammatic representation is output consistent with the placement representations.
Method And Apparatus For Specifying Addressability And Bus Connections In A Logic Design
Bart Reynolds - Seattle WA, US Cheng-I Chuang - Saratoga CA, US Chukwuweta Chukwudebe - Berkeley CA, US Sridhar Krishnamurthy - San Jose CA, US Damon McCormick - Mountain View CA, US Tom Shui - Mountain View CA, US Kai Zhu - Palo Alto CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F017/50
US Classification:
703 14, 710 66, 710307, 711170, 711202, 712300
Abstract:
In one embodiment, a method for specifying addressability in a memory-mapped device is disclosed. A data access primitive is used to model addressablity for the memory-mapped device. Addressability comprises an address matching function, a lane matching function and one or more bus connections. A first starting address for the memory-mapped device is specified. A first set of addressing matching function, lane matching function and one or more bus connections for the memory-mapped device is generated using the data access primitive and the first starting address.