Robert C Dockerty

US Patent:

40620409, Dec 6, 1977

Filed:

Mar 24, 1977

Appl. No.:

5/780943

Inventors:

Shakir Ahmed Abbas - Wappingers Falls NY
Robert Charles Dockerty - Highland NY

Assignee:

IBM Corporation - Armonk NY

International Classification:

H01L 2934

US Classification:

357 54

Abstract:

An improved field effect transistor structure which reduces a leakage phenomenon, termed the "sidewalk" effect, between the semiconductor substrate and a conductive silicon dioxide layer disposed over the substrate. The improvement comprises forming a layer of highly resistive, silicon dioxide or silicon oxynitride, which is between the conductive oxide and the silicon nitride layer which forms a portion of the gate insulator for the field effect transistor.

US Patent:

44097220, Oct 18, 1983

Filed:

Aug 29, 1980

Appl. No.:

6/182722

Inventors:

Robert C. Dockerty - Wappingers Falls NY
Paul L. Garbarino - Ridgefield CT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21225
H01L 21265

US Classification:

29571

Abstract:

Electrical contacts to diffused regions in a semiconductor substrate are made by a process which reduces the space needed in memory or logic cell layouts. The contacts are made such that they overlap, but are insulated from, adjacent conductors. The contacts are formed in a manner which avoids shorting of the diffused junctions to adjacent structures without being limited by lithographic overlay tolerances.

US Patent:

40104826, Mar 1, 1977

Filed:

Dec 31, 1975

Appl. No.:

5/645767

Inventors:

Shakir Ahmed Abbas - Wappingers Falls NY
Narasipur Gundappa Anantha - Hopewell Junction NY
Robert Charles Dockerty - Highland NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2948
H01L 2956
H01L 2964
H01L 2978

US Classification:

357 15

Abstract:

A non-volatile memory cell that includes a Schottky barrier diode, located over a sub-diffused line or region formed within the substrate, acting as the control element. Information is stored in the device by introducing electrons into a nitride-oxide interface located at the perimeter of the Schottky barrier junction. Thus, the injected electrons are subject to trapping in the nitride-oxide layer, causing depletion in the epi region adjoining the diode interface, thereby influencing the current carrying state of the device.

US Patent:

44307918, Feb 14, 1984

Filed:

Dec 30, 1981

Appl. No.:

6/335891

Inventors:

Robert C. Dockerty - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2122
H01L 21265
H01L 2128

US Classification:

29571

Abstract:

A method for fabricating a semiconductor integrated circuit structure having a sub-micrometer length device element is described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor within the substrate from one another. These semiconductor regions are designated to contain devices. At least one layer is formed over the device designated regions and etched to result in a patterned layer having substantially vertical sidewalls some of which sidewalls extend across certain of the device regions. A controlled sub-micrometer thickness sidewall layer is formed on these vertical sidewalls. The patterned layer is then removed which leaves the pattern of sub-micrometer thickness sidewall layer portions of which extend across certain of the device regions. The desired pattern of PN junctions are now formed in the substrate using for example diffusion or ion implantation techniques with the controlled thickness sub-micrometer layer used as a mask. The effect is the transfer of the submicron pattern into underlying region.

US Patent:

40444520, Aug 30, 1977

Filed:

Oct 6, 1976

Appl. No.:

5/729937

Inventors:

Shakir Ahmed Abbas - Wappingers Falls NY
Robert Charles Dockerty - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B01J 1700

US Classification:

29571

Abstract:

A process and the resulting structure for making metal oxide silicon field effect transistors and vertical bipolar transistors on the same semiconductor chip with the devices being dielectrically isolated from each other. The process does not require an epitaxial layer. The bipolar devices have utility as cross-chip or off-chip drivers or can be utilized for analog circuitry.

US Patent:

T9530053, Dec 7, 1976

Filed:

Jan 7, 1976

Appl. No.:

5/647284

Inventors:

Narasipur G. Anantha - Hopewell Junction NY
Robert C. Dockerty - Highland NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2948

US Classification:

357 15

Abstract:

A Schottky barrier diode having an encircling floating polycrystalline silicon gate which becomes charged upon avalanche breakdown of the diode. The gate is self-aligned with respect to the Schottky barrier diode metal so that the gate uniformly overhangs the depletion area in the semiconductor when the diode is reverse biased. The gate is insulated from the semiconductor material and from the metal by dielectric layers including silicon dioxide and silicon nitride.

US Patent:

39620522, Jun 8, 1976

Filed:

Apr 14, 1975

Appl. No.:

5/567656

Inventors:

Shakir A. Abbas - Wappingers Falls NY
Robert C. Dockerty - Highland NY
Michael R. Poponiak - Newburgh NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

C25F 300

US Classification:

2041293

Abstract:

A process for forming holes with precisely controlled dimension and position in monocrystalline silicon wafers wherein the holes are fabricated with vertical sides. In the preferred process, both sides of the silicon body are masked, opposite registered openings made in the masking layers, an impurity introduced through the openings into the body forming low resistivity regions, the body anodically etched through the openings until a porous silicon region is formed completely through the body, and subsequently removing the resultant porous silicon region with a silicon etchant.

US Patent:

40512738, Sep 27, 1977

Filed:

Nov 26, 1975

Appl. No.:

5/635523

Inventors:

Shakir Ahmed Abbas - Wappingers Falls NY
Robert Charles Dockerty - Highland NY

Assignee:

IBM Corporation - Armonk NY

International Classification:

B05D 512

US Classification:

427 86

Abstract:

An improved field effect transistor structure which reduces a leakage phenomenon, termed the "sidewalk" effect, between the semiconductor substrate and a conductive silicon dioxide layer disposed over the substrate. The improvement comprises forming a layer of highly resistive silicon dioxide or silicon oxynitride, which is between the conductive oxide and the silicon nitride layer which forms a portion of the gate insulator for the field effect transistor.