Edmundo Gabriel Delapuente

US Patent:

20150253378, Sep 10, 2015

Filed:

Mar 4, 2014

Appl. No.:

14/196873

Inventors:

- Tokyo, JP
Edmundo DeLaPuente - Cupertino CA, US

Assignee:

Advantest Corporation - Tokyo

International Classification:

G01R 31/28

Abstract:

An apparatus for providing a distributed and scalable number of power supplies used in automatic test equipment. The apparatus includes at least one Pin Electronics (PE) module comprising a plurality of PE channels. The apparatus includes at least one programmable power supply (PPS) module comprising a plurality of programmable power supply channels, wherein the at least one PPS module is remote from the at least one PE module. That apparatus includes a test site controller executing a test program comprising a plurality of test instructions delivered over the plurality of Pin Electronics (PE) channels and the plurality of programmable power supply (PPS) channels in order to test a plurality of devices under test (DUTs) in parallel.

US Patent:

20150137839, May 21, 2015

Filed:

Nov 19, 2013

Appl. No.:

14/084028

Inventors:

- Tokyo, JP
Takahiro Yasui - Gunma, JP
Edmundo Delapuente - Cupertino CA, US
Taichi Fukuda - Isesaki, JP

Assignee:

Advantest Corporation - Tokyo

International Classification:

G01R 1/00
G01R 31/00

US Classification:

32475001

Abstract:

A method for performing test site synchronization within automated test equipment (ATE) is presented. The method comprises controlling a plurality of test program controllers (TPCs) using a plurality of bridge controllers (BCs), wherein each TPC can initiate multiple asynchronous events. For an asynchronous event initiated by a TPC, raising a busy flag while the asynchronous event is not yet complete and de-asserting the busy flag when the asynchronous event is complete, wherein the asynchronous event corresponds to a task requiring an indeterminate amount of time. It also comprises generating a busy signal in the first BCs in response to receiving a busy flag from any of the plurality of TPCs, wherein the busy signal remains asserted while any of the plurality of TPCs asserts a busy flag. Finally, it comprises transmitting the busy signal to the plurality of TPCs, wherein the TPCs use the busy signal to synchronize operations.

US Patent:

20150135026, May 14, 2015

Filed:

Nov 11, 2013

Appl. No.:

14/077048

Inventors:

- Tokyo, JP
Edmundo DeLaPuente - Cupertino CA, US

Assignee:

Advantest Corporation - Tokyo

International Classification:

G11C 29/08

US Classification:

714718

Abstract:

A method for testing memory devices under test (DUTs) using automated test equipment (ATE) is presented. The method comprises retrieving a portion of raw test data from a memory device under test (DUT). It also comprises comparing the portion of raw test data with expected test data to determine failure information, wherein the failure information comprises information regarding failing bits generated by the memory DUT. Next, the method comprises utilizing paging to transfer data comprising the failure information to a filtering module and filtering out the failure information from transferred data using the filtering module. Further, it comprises updating a fail list using the failure information, wherein the fail list comprises address information for respective failing bits within the memory DUT. Finally, it comprises repeating all the prior steps for the next block of raw test data.