David F Mcmanigal

US Patent:

42187516, Aug 19, 1980

Filed:

Mar 7, 1979

Appl. No.:

6/018010

Inventors:

David F. McManigal - Stormville NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 750

US Classification:

364784

Abstract:

An absolute difference generator comprises an adder, an Exclusive-OR, two inverters and a latch. One input number is inverted, then presented to one input of the adder while the other input number is presented to the other input of the adder. The carry out line of the adder sets a latch, the output of which is fed back to the carry in line of the adder. The latch output is also combined with the adder output in an Exclusive-OR to control inversion of the adder output and produce the absolute difference between the input data.

US Patent:

47165464, Dec 29, 1987

Filed:

Jul 30, 1986

Appl. No.:

6/890662

Inventors:

William F. Beausoleil - Hopewell Junction NY
David F. McManigal - Stormville NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

364900

Abstract:

A memory organization for holding memory refresh data for a display uses input address selectors for memory modules for a segmented display to provide horizontal rotation of all data in the memory modules. On writing of vertical vectors, a logic tree using Exclusive ORs modifies memory address bits to provide tilt to the vertical vector and cause it to be orthogonal to horizontal vectors. Output data selectors read data from the memory modules to the display and derotate the data so that the display is restored to its original form.

US Patent:

60444541, Mar 28, 2000

Filed:

Feb 19, 1998

Appl. No.:

9/026328

Inventors:

Eric Mark Schwarz - Gardiner NY
Christopher A. Krygowski - Hopewell Junction NY
Timothy John Slegel - Staatsburg NY
David Frazelle McManigal - Red Hook NY
Mark Steven Farrell - Pleasant Valley NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9302
G06F 938

US Classification:

712201

Abstract:

IEEE compliant floating point unit mechanism allows variability in the execution of floating point operations according to the IEEE 754 standard and allowing variability of the standard to co-exist in hardware or in the combination of hardware and millicode. The FPU has a detector of special conditions which dynamically detects an event that the hardware execution of an IEEE compliant Binary Floating Point instruction will require millicode emulation. The complete set of events which millicode may emulate are predetermined early in the design process of the hardware. An exception handling unit assist millicode emulation by trapping the result of an exceptional condition without invoking the trap handler. When an exceptional condition is detected during execution, the IEEE 754 standard requires two different actions under control of a mask bit. If the mask bit is on, the result is written into an FPR and the trap handler is invoked.