Zunhang Yu Kasnavi

US Patent:

7952376, May 31, 2011

Filed:

Aug 28, 2008

Appl. No.:

12/231024

Inventors:

Zunhang Yu Kasnavi - Sunnyvale CA, US
Chung Fu - Sunnyvale CA, US
Ramraj Gottiparthy - Sunnyvale CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G01R 31/26

US Classification:

32476201, 32475001

Abstract:

Method and apparatus are disclosed related to testing and testability of adaptive equalization circuitry. Where an equalization circuit is provided in an IC, a modified internal loopback provides a testing signal. A local comparator circuit with flexible connectivity offers analog signal testing analysis in conjunction with a low-cost external tester. Flexible use and connectivity of the comparator and external connection points, and block isolation circuitry make accurate, faster, and lower cost testing methods possible.

US Patent:

8531196, Sep 10, 2013

Filed:

Feb 3, 2009

Appl. No.:

12/365147

Inventors:

Jaydev Amit Shelat - Santa Clara CA, US
Zunhang Yu Kasnavi - Sunnyvale CA, US
Dhananjay Srinivasa Raghavan - Campbell CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G01R 31/3187
G01R 31/26
G01R 31/28

US Classification:

3247503, 32476205

Abstract:

Programmable delay test circuitry is provided for testing a circuit under test on an integrated circuit. Delay test circuitry may use logic circuitry to output an error signal when a delay time provided by the circuit under test is greater than a characteristic time that may be programmed into the programmable delay test circuitry. Programmable delay test circuitry may use a logic gate to provide a pulse that has a pulse width equal to the delay of the delay circuitry. Programmable delay test circuitry may contain a programmable load that may be programmed to have a characteristic time. Programmable delay test circuitry may assert an error signal when the delay time is greater than the characteristic time of the test circuitry.

US Patent:

7620853, Nov 17, 2009

Filed:

Mar 5, 2007

Appl. No.:

11/714641

Inventors:

Zunhang Yu Kasnavi - Sunnyvale CA, US
Eng Ling Ho - Simpang Ampat, MY

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 11/00

US Classification:

714 42, 714725, 714719, 716 16, 716 4

Abstract:

Integrated circuits such as programmable logic device integrated circuits have configuration random-access memory elements. The configuration random-access memory elements are tested to determine whether any of the elements have resistive bridging faults at their outputs. During testing, a pattern of test configuration data is loaded into the configuration random-access memory elements. The programmable logic device is placed in user mode to clear programmable logic registers on the device. The configuration random-access memory elements are sensitized to the presence of resistive bridging faults by performing read operations. After sensitizing the configuration random-access memory elements, a tester applies test vectors to the programmable logic of the programmable logic device. As the test vectors are applied, the tester observes whether the programmable logic of the device is performing properly or has been affected by the presence of a resistive bridging fault.