Yuwen N Hsia

US Patent:

20130229926, Sep 5, 2013

Filed:

Mar 1, 2012

Appl. No.:

13/409491

Inventors:

Litai Lu - Fremont CA, US
Sheng Lin - Sunnyvale CA, US
Yuwen Hsia - Saratoga CA, US
Menping Chang - Cupertino CA, US

Assignee:

MICREL, INC. - San Jose CA

International Classification:

H04L 12/66
H04L 12/26

US Classification:

370249, 370463

Abstract:

A network device includes a physical layer transceiver configured to receive incoming data on a data link at an input clock rate and to store the incoming data in a buffer. The physical layer transceiver includes a Media Independent Interface (MII) controller configured to receive the incoming data stored in the buffer and to transmit the incoming data over a MII bus based on a MII clock where the MII clock is a spread spectrum clock. The network device further includes a Media Access Control (MAC) device configured to receiving incoming data from the physical layer transceiver over the MII bus where the incoming data is clocked by the spread spectrum MII clock.

US Patent:

59031808, May 11, 1999

Filed:

Jul 24, 1997

Appl. No.:

8/900084

Inventors:

Yuwen Hsia - Saratoga CA
Sarathy Sribhashyam - Sunnyvale CA

Assignee:

S3 Incorporated - Santa Clara CA

International Classification:

H03L5/00

US Classification:

327333

Abstract:

A voltage tolerant bus hold latch comprises a first buffer transistor, a sense transistor, a low voltage latch, a node voltage controller and a pull-up circuit. The low voltage latch is coupled to the input by the first transistor. The node voltage controller is coupled to the input by the sense transistor. The node voltage controller has a pair of additional inputs coupled to the output of the low voltage latch. The output of the node voltage controller is coupled to control the operation of the pull-up circuit. The pull-up circuit is coupled to the supply voltage for the lower voltage circuitry, and has another control input coupled to the output of the low voltage latch. The output of the pull-up circuit is coupled to the input of the voltage tolerant latch. The pull-up circuit is selectively activated to pull the input of the latch to a high voltage level. The node voltage controller acts as voltage divider to maintain a voltage difference across the gate-to-drain of the pull-up circuit within the operating tolerance of the pull-up circuit (Vtp+2*Vtn).

US Patent:

59735112, Oct 26, 1999

Filed:

Jan 5, 1999

Appl. No.:

9/225650

Inventors:

Yuwen Hsia - San Jose CA
Sarathy Sribhashyam - Sunnyvale CA

Assignee:

S3 Incorporated - Santa Clara CA

International Classification:

H03K 190185

US Classification:

326 81

Abstract:

A voltage tolerant input/output buffer comprises a current mirror, a voltage sensing and isolating circuit, an output pull-up transistor, and an output pull-down transistor. The output pull-up transistor preferably has its gate coupled to the voltage sensing and isolating circuit to receive signals from the lower voltage circuitry, its source coupled to the supply voltage for the lower operating voltage circuitry, and its drain provides the output for connection to the higher voltage circuitry. The voltage sensing and isolating circuit is coupled between the gate and the drain of the output pull-up transistor. The current mirror is coupled to ground and to the voltage sensing and isolating circuit. The output pull-down transistor has its drain coupled to the voltage sensing and isolating circuit, it source coupled to ground, and its gate coupled to receive pull down signals from the lower operating voltage circuit. The current mirror and the voltage sensing and isolating circuit are provided such that as the higher voltage circuit applies a high supply voltage to the drain of the pull-up output transistor, the pull-up output transistor is able to transition to a state at the supply voltage of the lower circuit and sink the current such that the buffer operates properly and correctly, unaffected by the application of the higher operating supply voltage to the drain of the pull-up transistor.

US Patent:

59072490, May 25, 1999

Filed:

Feb 19, 1997

Appl. No.:

8/801002

Inventors:

Yuwen Hsia - San Jose CA
Sarathy Sribhashyam - Sunnyvale CA

Assignee:

S3 Incorporated - Santa Clara CA

International Classification:

H03K 190185

US Classification:

326 81

Abstract:

A voltage tolerant input/output buffer comprises a current mirror, a voltage sensing and isolating circuit, an output pull-up transistor, and an output pull-down transistor. The output pull-up transistor preferably has its gate coupled to the voltage sensing and isolating circuit to receive signals from the lower voltage circuitry, its source coupled to the supply voltage for the lower operating voltage circuitry, and its drain provides the output for connection to the higher voltage circuitry. The voltage sensing and isolating circuit is coupled between the gate and the drain of the output pull-up transistor. The current mirror is coupled to ground and to the voltage sensing and isolating circuit. The output pull-down transistor has its drain coupled to the voltage sensing and isolating circuit, it source coupled to ground, and its gate coupled to receive pull down signals from the lower operating voltage circuit. The current mirror and the voltage sensing and isolating circuit are provided such that as the higher voltage circuit applies a high supply voltage to the drain of the pull-up output transistor, the pull-up output transistor is able to transition to a state at the supply voltage of the lower circuit and sink the current such that the buffer operates properly and correctly, unaffected by the application of the higher operating supply voltage to the drain of the pull-up transistor.