Yuval Cassuto from Moraga, CA, age 49

Codes For Limited Magnitude Asymmetric Errors In Flash Memories
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US Patent:

8296623, Oct 23, 2012
Filed:

Jan 4, 2008
Appl. No.:

11/969846
Inventors:

Yuval Cassuto - Pasadena CA, US
Jehoshua Bruck - La Canada CA, US
Moshe Schwartz - Pasadena CA, US
Vasken Bohossian - Pasadena CA, US
Assignee:

California Institute of Technology - Pasadena CA
International Classification:

H03M 13/00
G11C 29/00
US Classification:

714759, 714773
Abstract:

Error correction is tailored for the use of an ECC for correcting asymmetric errors with low magnitude in a data device, with minimal modifications to the conventional data device architecture. The technique permits error correction and data recovery to be performed with reduced-size error correcting code alphabets. For particular cases, the technique can reduce the problem of constructing codes for correcting limited magnitude asymmetric errors to the problem of constructing codes for symmetric errors over small alphabets. Also described are speed up techniques for reaching target data levels more quickly, using more aggressive memory programming operations.

Information Storage Device With Multiple-Use Fields In Servo Pattern
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US Patent:

8422161, Apr 16, 2013
Filed:

Dec 18, 2009
Appl. No.:

12/653863
Inventors:

Yuval Cassuto - Sunnyvale CA, US
Jonathan Darrel Coker - Rochester MN, US
David Timothy Flynn - Mantorville MN, US
Assignee:

HGST Netherlands B.V. - Amsterdam
International Classification:

G11B 5/596
US Classification:

360 7708
Abstract:

An embodiment of the present invention implements some or all major servo subfunctions for a storage device in integrated servo fields comprising sequences of encoded bits having selected mathematical properties. The integrated servo field is composed of a number of encoded sequences, which are members of a selected sequence set that is constrained to preferably provide some or all of the following functions: the Servo Track Mark (STM), the Position Error Signal (PES) and positional information such as the track-ID. In one embodiment the plurality sequences encoding a location identifier such as a track-ID are distributed across a set of servo wedges. A method of encoding the location identifier using a Chinese Remainder Theorem is described.

Implementing Secure Erase For Solid State Drives
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US Patent:

20110154060, Jun 23, 2011
Filed:

Dec 17, 2009
Appl. No.:

12/640730
Inventors:

Cyril Guyot - San Jose CA, US
Zvonimir Z. Bandic - San Jose CA, US
Yuval Cassuto - Sunnyvale CA, US
Adam Michael Espeseth - Rochester MN, US
Marco Sanvido - Belmont CA, US
Assignee:

Hitachi Global Storage Technologies Netherlands B.V. - Amsterdam
International Classification:

G06F 12/14
G06F 21/24
US Classification:

713193, 380277
Abstract:

A method and apparatus are provided for implementing secure erase for solid state drives (SSDs). An encryption key is used to encrypt data being written to SSD. A controller identifies a key storage option, and responsive to the identified key storage option, stores a key for data encryption and decryption. The controller deletes the key within the SSD responsive to the identified key storage option, ensuring that once the key is deleted, the key is not recoverable and data is effectively erased.

Training Ensemble Models To Improve Performance In The Presence Of Unreliable Base Classifiers
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US Patent:

20210097446, Apr 1, 2021
Filed:

Jun 1, 2020
Appl. No.:

16/889644
Inventors:

- San Jose CA, US
Yuval CASSUTO - Sunnyvale CA, US
International Classification:

G06N 20/20
G06F 16/28
G06N 7/00
G06N 5/00
Abstract:

A system and method for training base classifiers in a boosting algorithm includes optimally training base classifiers considering an unreliability model, and then using a scheme with an aggregator decoder that reverse-flips inputs using inter-classifier redundancy introduced in training.

Computational Resource Allocation In Ensemble Machine Learning Systems
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US Patent:

20210073036, Mar 11, 2021
Filed:

Sep 6, 2019
Appl. No.:

16/563776
Inventors:

- San Jose CA, US
Yuval Cassuto - Sunnyvale CA, US
Robert Mateescu - San Jose CA, US
Cyril Guyot - San Jose CA, US
Assignee:

Western Digital Technologies, Inc. - San Jose CA
International Classification:

G06F 9/50
G06F 13/16
G06N 3/04
G06K 9/62
Abstract:

A system and method for allocating computational resources includes a plurality of classifiers, a memory array, and a memory controller to allocate memory from the memory array to each of the plurality of classifier. The system and method also include an optimization processor to determine an optimized bit precision value for at least one of the plurality of classifiers based upon a relative importance of the plurality of classifiers. The memory controller allocates the memory from the memory array to the plurality of classifiers based upon the determined optimized bit precision value.

Yuval Cassuto