Vikram S Santurkar from 360 Kiely Blvd #235, San Jose, CA 95129, age 54

Us Patents

Multiple Size Memories In A Programmable Logic Device
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US Patent:

6720796, Apr 13, 2004
Filed:

May 6, 2002
Appl. No.:

10/140311
Inventors:

Srinivas Reddy - Fremont CA
David Jefferson - Morgan Hill CA
Christopher F. Lane - San Jose CA
Vikram Santurkar - San Jose CA
Richard Cliff - Los Altos CA
Assignee:

Altera Corporation - San Jose CA
International Classification:

H03K 19177
US Classification:

326 39, 326 41, 326 40
Abstract:

A programmable logic device (PLD) includes a first memory block and at least a second memory block, where the two memory blocks have different memory sizes.

Versatile Logic Element And Logic Array Block
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US Patent:

6937064, Aug 30, 2005
Filed:

Oct 24, 2002
Appl. No.:

10/280723
Inventors:

David M. Lewis - Toronto, CA
Paul Leventis - Toronto, CA
Andy L. Lee - San Jose CA, US
Henry Kim - San Jose CA, US
Bruce Pedersen - San Jose CA, US
Chris Wysocki - Toronto, CA
Christopher F. Lane - San Jose CA, US
Alexander Marquardt - Toronto, CA
Vikram Santurkar - San Jose CA, US
Vaughn Betz - Toronto, CA
Assignee:

Altera Corporation - San Jose CA
International Classification:

H03K019/177
US Classification:

326 40, 326 39, 326 41
Abstract:

An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs.

Programmable Logic Device With Redundant Circuitry
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US Patent:

6965249, Nov 15, 2005
Filed:

May 30, 2002
Appl. No.:

10/159581
Inventors:

Christopher Lane - San Jose CA, US
Ketan Zaveri - San Jose CA, US
Hyun Yi - San Jose CA, US
Giles Powell - Alameda CA, US
Paul Leventis - Ontario, CA
David Jefferson - Morgan Hill CA, US
David Lewis - Ontario, CA
Triet Nguyen - San Jose CA, US
Vikram Santurkar - San Jose CA, US
Michael Chan - Ontario, CA
Andy Lee - San Jose CA, US
Brian Johnson - Sunnyvale CA, US
David Cashman - Ontario, CA
Assignee:

Altera Corporation - San Jose CA
International Classification:

H03K019/177
US Classification:

326 10, 326 9, 326 41
Abstract:

A programmable logic device and associated method is provided with repairable regions. In one aspect, general routing interconnect lines are segmented within repairable regions. In another aspect, IO bus lines and associated circuitry are provided that accommodate redundancy in a staggered segmented architecture. In another aspect, a dedicated routing architecture between particular logic regions accommodates shifting to define and utilize repairable regions. Principles of other aspects are illustrated and described in the context of several exemplary embodiments of aspects of the invention.

Multiple Size Memories In A Programmable Logic Device
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US Patent:

7161381, Jan 9, 2007
Filed:

Feb 25, 2004
Appl. No.:

10/787818
Inventors:

Srinivas Reddy - Fremont CA, US
David Jefferson - Morgan Hill CA, US
Christopher F. Lane - San Jose CA, US
Vikram Santurkar - San Jose CA, US
Richard Cliff - Los Altos CA, US
Assignee:

Altera Corporation - San Jose CA
International Classification:

H03K 19/177
US Classification:

326 39, 326 41, 326 47
Abstract:

A programmable logic device (PLD) includes a first memory block and at least a second memory block, where the two memory blocks have different memory sizes.

Versatile Logic Element And Logic Array Block
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US Patent:

7218133, May 15, 2007
Filed:

Feb 2, 2005
Appl. No.:

11/050111
Inventors:

David M. Lewis - Toronto, CA
Paul Leventis - Toronto, CA
Andy L. Lee - San Jose CA, US
Henry Kim - San Jose CA, US
Bruce Pedersen - Sunnyvale CA, US
Chris Wysocki - Toronto, CA
Christopher F. Lane - San Jose CA, US
Alexander Marquardt - Toronto, CA
Vikram Santurkar - Fremont CA, US
Vaughn Timothy Betz - Toronto, CA
Assignee:

Altera Corporation - San Jose CA
International Classification:

H03K 19/003
US Classification:

326 10, 326 9, 326 39, 326 41
Abstract:

An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs.

Method Of Reducing Leakage Current Using Sleep Transistors In Programmable Logic Device
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US Patent:

7355440, Apr 8, 2008
Filed:

Dec 23, 2005
Appl. No.:

11/318324
Inventors:

Vikram Santurkar - Fremont CA, US
Hyun Mo Yi - Mountain View CA, US
Christopher F. Lane - San Jose CA, US
Assignee:

Altera Corporation - San Jose CA
International Classification:

H03K 19/173
G06F 7/38
US Classification:

326 38, 326 41
Abstract:

A programmable logic device (PLD) having minimal leakage current for inactive logic blocks is provided. The PLD includes an array of logic blocks. Among the array of logic blocks, one of the array of logic blocks monitors the level of activity of each of the remaining logic blocks. The level of activity may be monitored by observing the input and output pin of the logic blocks. The PLD further includes a plurality of driven wires defining a routing pattern between the array of logic blocks. When one of the array of logic blocks detect inactivity in any one of the remaining logic blocks for a certain duration, the one of the array logic blocks transmits a signal invoking a sleep mode for the inactive logic blocks. A sleep transistor with a threshold voltage level that is capable minimizing the leakage current is associated with each of the remaining block. The gate of the sleep transistor receives the signal transmitted by one of the array logic blocks and the signal switches off the sleep transistor.

Techniques For Serially Transmitting On-Chip Termination Control Signals
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US Patent:

7391229, Jun 24, 2008
Filed:

Feb 18, 2006
Appl. No.:

11/356867
Inventors:

Vikram Santurkar - Fremont CA, US
Hyun Mo Yi - Sunnyvale CA, US
Quyen Doan - Milpitas CA, US
Assignee:

Altera Corporation - San Jose CA
International Classification:

H03K 19/003
US Classification:

326 30, 326 83, 326 86, 327108
Abstract:

Techniques are provided for controlling on-chip termination (OCT) impedance using OCT calibration blocks that serially transmit OCT control signals to input/output (IO) blocks. The OCT control signals are serially transmitted through a shared conductor. An OCT calibration block can transmit OCT control signals to one or multiple IO blocks. The IO blocks can be programmed to select OCT control signals from one of the calibration blocks. Enable signals enable one or more of the IO blocks to receive the selected OCT control signals. The OCT control signals are used to control the on-chip termination impedance at one or more IO buffers.

Techniques For Sensing Temperature And Automatic Calibration On Integrated Circuits
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US Patent:

7410293, Aug 12, 2008
Filed:

May 17, 2006
Appl. No.:

11/383937
Inventors:

Vikram Santurkar - Fremont CA, US
Quyen Doan - Milpitas CA, US
Assignee:

Altera Corporation - San Jose CA
International Classification:

G01K 7/00
US Classification:

374178, 374170, 327512
Abstract:

Techniques are provided for sensing the temperature of an integrated circuit (IC). A diode is provided on an IC. The voltage across the diode varies with the temperature of the IC. A feedback loop is coupled around the diode to monitor the voltage across the diode. The feedback loop contains a comparator and logic circuitry that outputs a digital code. The digital code varies in response to changes in the diode voltage. The value of the digital code can be used to determine the temperature on the IC. Techniques are also provided for automatically calibrating a temperature sensing circuit to compensate for inaccuracies caused by variations in process, temperature, and supply voltage. A calibration circuit is added to the feedback loop in the temperature sensor. The calibration circuit generates an offset code that is used to adjust the digital code to compensate for variations in temperature, process, and supply voltage.