Vijay Bharat Nijhawan

US Patent:

7500067, Mar 3, 2009

Filed:

Mar 29, 2006

Appl. No.:

11/392272

Inventors:

Madhusudhan Rangarajan - Round Rock TX, US
Vijay B. Nijhawan - Austin TX, US

Assignee:

Dell Products L.P. - Round Rock TX

International Classification:

G06F 12/00

US Classification:

711147, 711148, 711165, 711205

Abstract:

The present disclosure describes systems and methods for allocating memory in a multiprocessor computer system such as a non-uniform memory access (NUMA) machine having distribute shared memory. The systems and methods include allocating memory to input-output devices (I/O devices) based at least in part on which memory resource is physically closest to a particular I/O device. Through these systems and methods memory is allocated more efficiently in a NUMA machine. For example, allocating memory to an I/O device that i80s on the same node as a memory resource, reduces memory access time thereby maximizing data transmission. The present disclosure further describes a system and method for improving performance in a multiprocessor computer system by utilizing a pre-programmed device affinity table. The system and method includes listing the memory resources physically closest to each I/O device and accessing the device table to determine the closest memory resource to a particular I/O device. The system and method further includes directing a device driver to transmit data between the I/O device and the closest memory resource.

US Patent:

7577813, Aug 18, 2009

Filed:

Oct 11, 2005

Appl. No.:

11/247036

Inventors:

Vijay B. Nijhawan - Austin TX, US
Saurabh Gupta - Federal Way WA, US
Wuxian Wu - Round Rock TX, US

Assignee:

Dell Products L.P. - Round Rock TX

International Classification:

G06F 12/00

US Classification:

711170, 711147, 711148, 711171, 711172, 711173

Abstract:

A system and method is disclosed for enumerating multi-level processor-memory affinities for non-uniform memory access systems. A processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in an information-handling system is calculated using at least two characteristics relating to memory-access speed that describe how the microprocessors and memory units are arranged in the information-handling system. The information-handling system then performs an algorithm on each processor-memory affinity hierarchy to obtain processor-memory affinity values in the information-handling system, and populates a table using the processor-memory affinity values. An operating system in the information-handling system can use the table to allocate memory units among microprocessors in the information-handling system.

US Patent:

7596648, Sep 29, 2009

Filed:

Mar 8, 2007

Appl. No.:

11/683450

Inventors:

Madhusudhan Ramgarajan - Round Rock TX, US
Vijay Nijhawan - Austin TX, US

Assignee:

Dell Products L.P. - Round Rock TX

International Classification:

G06F 13/24

US Classification:

710263, 710268, 714 5, 714 13

Abstract:

An information handling system recovers from memory errors associated with a memory unit that supports operation of an SMI handler by using another memory unit to support operation of the SMI handler. For example, if an SMI handler detects an error associated with a DIMM that supports operation of the SMI handler, then an SMI handler location module moves the SMI handler to another DIMM. For instance, a jump command is activated to jump to a pre-existing copy of the SMI handler stored at another DIMM. As another example, a relocation of the SMI handler to another DIMM is performed by changing address information used by the chipset and CPUs to run the SMI handler.

US Patent:

7620860, Nov 17, 2009

Filed:

Sep 7, 2007

Appl. No.:

11/851683

Inventors:

Vijay Nijhawan - Austin TX, US

Assignee:

Dell Products, LP - Round Rock TX

International Classification:

G11C 29/00

US Classification:

714723, 714704

Abstract:

An information handling system is disclosed and can include a processor and a memory coupled to the processor. Further, the system can include a system reserved area that is accessible to the processor. The system reserved area can include a physical memory fault table having a plurality of bits and each bit in the physical memory fault table can represent an equal block of the memory.

US Patent:

7694125, Apr 6, 2010

Filed:

Dec 1, 2006

Appl. No.:

11/565941

Inventors:

Vijay Nijhawan - Austin TX, US
Allen C. Wynn - Round Rock TX, US

Assignee:

Dell Products, LP - Round Rock TX

International Classification:

G06F 15/177

US Classification:

713100, 713 1, 713 2

Abstract:

A method of booting an operating system for use with an information handling system includes identifying an operating system dependent configuration, and determining an operating system type of the operating system. Further, the method includes changing the operating system dependent configuration in response to the operating system type.

US Patent:

7716504, May 11, 2010

Filed:

Jul 13, 2006

Appl. No.:

11/457172

Inventors:

Vijay B. Nijhawan - Austin TX, US
Alok Pant - Cedar Park TX, US

Assignee:

Dell Products L.P. - Round Rock TX

International Classification:

G06F 1/26
G06F 1/32

US Classification:

713320

Abstract:

A method for adjusting power management setting of the operating system while the system is in a sleep state. When a user attaches or removes power to the information handling system while the system is in a standby mode of operation, the sleep state system generates a wakeup event. During the resume process, the operating system checks a current power state of the information handling system and compares the current power state to the power state settings present when the information handling system entered the sleep state, resets the power state settings if necessary and then causes the information handling system to reenter the sleep state.

US Patent:

7721034, May 18, 2010

Filed:

Sep 29, 2006

Appl. No.:

11/540805

Inventors:

Vijay Nijhawan - Austin TX, US
Madhusudhan Rangarajan - Round Rock TX, US
Wuxian Wu - Round Rock TX, US

Assignee:

Dell Products L.P. - Round Rock TX

International Classification:

G06F 13/24

US Classification:

710266, 710268

Abstract:

A system and method is disclosed for managing system management interrupts in a multiprocessor system. The system described herein includes multiple processors, each of which may be directly coupled to memory. A primary processor will recognize the initiation of a system management interrupt. The primary processor will write a reason code to a storage location and set a watchdog timer, the expiration of which causes all of the processors of the system to enter a system management mode. After all of the processors have entered system management mode, it is determined if the reason code of the storage location corresponds to certain software-based system management interrupts. If so, the system management interrupt is handled by the local processors. Following the handling of the system management interrupt by the local processor, a signal is sent to each of the other processors to cause the processors to exit system management mode.

US Patent:

7797473, Sep 14, 2010

Filed:

Jun 5, 2008

Appl. No.:

12/133580

Inventors:

Madhusudhan Rangarajan - Round Rock TX, US
Vijay Nijhawan - Austin TX, US

Assignee:

Dell Products, LP - Round Rock TX

International Classification:

G06F 13/24

US Classification:

710260

Abstract:

An information handling system includes a first processor device to execute a handler in response to a system management interrupt (SMI). While the first processor device executes the SMI handler, a second processor device of the information handling system can continue to execute software and perform other operations in a normal mode. When the first processor device accesses a shared resource in executing the SMI handler, an SMI trap for the shared resource is enabled. In response to the second processor device triggering the SMI trap by accessing the shared resource, the second processor device enters an SMI mode, thereby suspending execution of software and other operations. Accordingly, a second processor device is allowed to continue normal operations while a first processor device executes an SMI handler, improving system efficiency while preventing shared resource conflicts.

Address:

10221 Chestnut Rdg Rd, Austin, TX 78726

VIN:

4T1BE46K67U012503

Make:

TOYOTA

Model:

CAMRY

Year:

2007