Udayan Ganguly

US Patent:

7972933, Jul 5, 2011

Filed:

Mar 29, 2010

Appl. No.:

12/748523

Inventors:

Christopher S. Olsen - Fremont CA, US
Johanes Swenberg - Los Gatos CA, US
Udayan Ganguly - Sunnyvale CA, US
Theresa Kramer Guarini - San Jose CA, US
Yonah Cho - Sunnyvale CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/76

US Classification:

438431, 257E21079, 257E21267, 257E21301, 438770, 438911

Abstract:

Methods of forming semiconductor devices are provided herein. In some embodiments, a method of forming a semiconductor device may include providing a substrate having an oxide surface and a silicon surface; forming a nitrogen-containing layer on exposed portions of both the oxide and silicon surfaces; and oxidizing the nitrogen-containing layer to selectively remove the nitrogen-containing layer from atop the oxide surface. In some embodiments, an oxide layer is formed atop a remaining portion of the nitrogen-containing layer formed on the silicon feature. In some embodiments, the oxide surface is an exposed surface of a shallow trench isolate region (STI) disposed adjacent to one or more floating gates of a semiconductor device. In some embodiments, the silicon surface is an exposed surface of a silicon or polysilicon floating gate of a semiconductor device.

US Patent:

8163626, Apr 24, 2012

Filed:

Jun 15, 2010

Appl. No.:

12/815659

Inventors:

David Chu - Campbell CA, US
Theresa Kramer Guarini - San Jose CA, US
Yonah Cho - Sunnyvale CA, US
Udayan Ganguly - San Jose CA, US
Lucien Date - Ottignies-Louvain-La-Neuve, BE

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/76

US Classification:

438431, 257E21079, 257E21267, 257E21301, 438770, 438911

Abstract:

Embodiments described herein generally relate to flash memory devices and methods for manufacturing flash memory devices. In one embodiment, a method for selective removal of nitrogen from the nitrided areas of a substrate is provided. The method comprises positioning a substrate comprising a material layer disposed adjacent to an oxide containing layer in a processing chamber, exposing the substrate to a nitridation process to incorporate nitrogen onto the material layer and the exposed areas of the oxide containing layer, and exposing the nitrided material layer and the nitrided areas of the oxide containing layer to a gas mixture comprising a quantity of a hydrogen containing gas and a quantity of an oxygen containing gas to selectively remove nitrogen from the nitrided areas of the oxide containing layer relative to the nitrided material layer using a radical oxidation process.

US Patent:

8198671, Jun 12, 2012

Filed:

Apr 22, 2010

Appl. No.:

12/799365

Inventors:

Christopher Sean Olsen - Fremont CA, US
Tze Wing Poon - Sunnyvale CA, US
Udayan Ganguly - Sunnyvale CA, US
Johanes Swenberg - Los Gatos CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 29/792
H01L 21/336

US Classification:

257324, 257E29309, 257E21423, 438287, 438954

Abstract:

A flash memory device comprises a substrate comprising silicon with a silicon dioxide layer thereon. A silicon-oxygen-nitrogen layer is on the silicon dioxide layer, and the silicon-oxygen-nitrogen layer comprises a shaped concentration level profile of oxygen through the thickness of the layer. A blocking dielectric layer is on the silicon-oxygen-nitrogen layer, and a gate electrode is on the blocking dielectric layer. Oxygen ions can be implanted into a silicon nitride layer to form the silicon-oxygen-nitrogen layer.

US Patent:

7262991, Aug 28, 2007

Filed:

Jun 30, 2005

Appl. No.:

11/174128

Inventors:

Yuegang Zhang - Cupertino CA, US
Udayan Ganguly - Ithaca NY, US
Edwin Kan - Saratoga CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 11/34

US Classification:

36518501, 257315, 257316, 257 9, 257E5104, 365151

Abstract:

An embodiment is a transistor for non-volatile memory that combines nanocrystal and nanotube paradigm shifts. In particular an embodiment is a transistor-based non-volatile memory element that utilizes a carbon nanotube channel region and nanocrystal charge storage regions. Such a combination enables a combination of low power, low read and write voltages, high charge retention, and high bit density. An embodiment further exhibits a large memory window and a single-electron drain current.

US Patent:

20070064478, Mar 22, 2007

Filed:

Nov 14, 2006

Appl. No.:

11/599643

Inventors:

Yuegang Zhang - Cupertino CA, US
Udayan Ganguly - Ithaca NY, US
Edwin Kan - Saratoga CA, US

International Classification:

G11C 16/04

US Classification:

365185010

Abstract:

An embodiment is a transistor for non-volatile memory that combines nanocrystal and nanotube paradigm shifts. In particular an embodiment is a transistor-based non-volatile memory element that utilizes a carbon nanotube channel region and nanocrystal charge storage regions. Such a combination enables a combination of low power, low read and write voltages, high charge retention, and high bit density. An embodiment further exhibits a large memory window and a single-electron drain current.

US Patent:

20100062603, Mar 11, 2010

Filed:

Sep 11, 2009

Appl. No.:

12/558370

Inventors:

Udayan Ganguly - Sunnyvale CA, US
Yoshita Yokota - San Jose CA, US
Jing Tang - Santa Clara CA, US
Sunderraj Thirupapuliyur - San Jose CA, US
Christopher Sean Olsen - Fremont CA, US
Shiyu Sun - San Jose CA, US
Tze Wing Poon - Sunnyvale CA, US
Wei Liu - San Jose CA, US
Johanes Swenberg - Los Gatos CA, US
Vicky U. Nguyen - Milpitas CA, US
Swaminathan Srinivasan - Pleasanton CA, US
Jacob Newman - Palo Alto CA, US

International Classification:

H01L 21/311
H01L 21/28

US Classification:

438694, 438594, 257E21257, 257E21209

Abstract:

Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.

US Patent:

20110061810, Mar 17, 2011

Filed:

Mar 10, 2010

Appl. No.:

12/720957

Inventors:

Udayan Ganguly - Sunnyvale CA, US
Joseph M. Ranish - San Jose CA, US
Aaron M. Hunter - Santa Cruz CA, US
Jing Tang - Cupertino CA, US
Christopher S. Olsen - Fremont CA, US
Matthew D. Scotney-Castle - Morgan Hill CA, US
Vicky Nguyen - Milpitas CA, US
Swaminathan Srinivasan - Pleasanton CA, US
Johanes F. Swenberg - Los Gatos CA, US
Anchuan Wang - San Jose CA, US
Nitin K. Ingle - Santa Clara CA, US
Manish Hemkar - Sunnyvale CA, US
Jose A. Marin - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/3065

US Classification:

15634527

Abstract:

Apparatus and methods for the manufacture of semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. Disclosed are various single chambers configured to form and/or shape a material layer by oxidizing a surface of a material layer to form an oxide layer; removing at least some of the oxide layer by an etching process; and cyclically repeating the oxidizing and removing processes until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.

US Patent:

20110061812, Mar 17, 2011

Filed:

Mar 10, 2010

Appl. No.:

12/720926

Inventors:

Udayan Ganguly - Sunnyvale CA, US
Yoshitaka Yokota - San Jose CA, US
Christopher S. Olsen - Fremont CA, US
Matthew D. Scotney-Castle - Morgan Hill CA, US
Vicky Nguyen - Milpitas CA, US
Swaminathan Srinivasan - Pleasanton CA, US
Wei Liu - San Jose CA, US
Johanes F. Swenberg - Los Gatos CA, US
Jose A. Marin - San Jose CA, US
Jacob Newman - Palo Alto CA, US
Stephen C. Hickerson - Hollister CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/465

US Classification:

15634534, 1563451, 257E21485

Abstract:

Apparatus and methods for the manufacture of semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. Disclosed are various single chambers configured to form and/or shape a material layer by oxidizing a surface of a material layer to form an oxide layer; removing at least some of the oxide layer by an etching process; and cyclically repeating the oxidizing and removing processes until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.