Todd E Takken

US Patent:

7174434, Feb 6, 2007

Filed:

Feb 25, 2002

Appl. No.:

10/468994

Inventors:

Matthias A. Blumrich - Ridgefield CT, US
Dong Chen - Croton On Hudson NY, US
Paul W. Coteus - Yorktown Heights NY, US
Alan G. Gara - Mount Kisco NY, US
Mark E. Giampapa - Irvington NY, US
Philip Heidelberger - Cortlandt Manor NY, US
Dirk Hoenicke - Ossining NY, US
Martin Ohmacht - Brewster NY, US
Todd E. Takken - Mount Kisco NY, US
Pavlos M. Vranas - Bedford Hills NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/12

US Classification:

711152, 711163

Abstract:

A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm.

US Patent:

7185226, Feb 27, 2007

Filed:

Feb 25, 2002

Appl. No.:

10/469002

Inventors:

Dong Chen - Croton On Hudson NY, US
Paul W. Coteus - Yorktown Heights NY, US
Alan G. Gara - Mount Kisco NY, US
Todd E. Takken - Mount Kisco NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/20
G06F 11/00

US Classification:

714 13, 714 10, 712 12, 712 15

Abstract:

A multiprocessor, parallel computer is made tolerant to hardware failures by providing extra groups of redundant standby processors and by designing the system so that these extra groups of processors can be swapped with any group which experiences a hardware failure. This swapping can be under software control, thereby permitting the entire computer to sustain a hardware failure but, after swapping in the standby processors, to still appear to software as a pristine, fully functioning system.

US Patent:

7186924, Mar 6, 2007

Filed:

Oct 21, 2003

Appl. No.:

10/690113

Inventors:

Ehood Geva - Palo Alto CA, US
Todd E. Takken - Brewster NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 1/00

US Classification:

174258, 174257, 174255, 174262, 174260

Abstract:

A trace cover suitable for shielding a conductive trace on a top layer of a circuit board. The trace cover includes a dielectric body disposed substantially over the conductive trace, side shielding perpendicular to the direction of the conductive trace and substantially parallel to the length of the conductive trace, and top shielding disposed on the top surface of the body. The side shielding and top shielding are electrically coupled with the at least one circuit ground of the circuit board.

US Patent:

7305487, Dec 4, 2007

Filed:

Feb 25, 2002

Appl. No.:

10/469001

Inventors:

Matthias A. Blumrich - Ridgefield CT, US
Dong Chen - Croton On Hudson NY, US
Paul W. Coteus - Yorktown Heights NY, US
Alan G. Gara - Mount Kisco NY, US
Mark E. Giampapa - Irvington NY, US
Philip Heidelberger - Cortlandt Manor NY, US
Todd E. Takken - Mount Kisco NY, US
Pavlos M. Vranas - Bedford Hills NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/173

US Classification:

709238, 709240, 709220, 370389, 370392

Abstract:

In a massively parallel computing system having a plurality of nodes configured in m multi-dimensions, each node including a computing device, a method for routing packets towards their destination nodes is provided which includes generating at least one of a 2m plurality of compact bit vectors containing information derived from downstream nodes. A multilevel arbitration process in which downstream information stored in the compact vectors, such as link status information and fullness of downstream buffers, is used to determine a preferred direction and virtual channel for packet transmission. Preferred direction ranges are encoded and virtual channels are selected by examining the plurality of compact bit vectors. This dynamic routing method eliminates the necessity of routing tables, thus enhancing scalability of the switch.

US Patent:

7383490, Jun 3, 2008

Filed:

Apr 14, 2005

Appl. No.:

11/106069

Inventors:

Gheorghe Almasi - Ardsley NY, US
Matthias Augustin Blumrich - Ridgefield CT, US
Dong Chen - Croton-On-Hudson NY, US
Paul Coteus - Yorktown NY, US
Alan Gara - Mount Kisco NY, US
Mark E. Giampapa - Irvington NY, US
Philip Heidelberger - Cortlandt Manor NY, US
Dirk I. Hoenicke - Ossining NY, US
Sarabjeet Singh - Mississauga, CA
Burkhard D. Steinmacher-Burow - Wernau, DE
Todd Takken - Brewster NY, US
Pavlos Vranas - Bedford Hills NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00
H03M 13/00

US Classification:

714800, 714770, 714758, 714100

Abstract:

Methods and apparatus perform fault isolation in multiple node computing systems using commutative error detection values for—example, checksums—to identify and to isolate faulty nodes. When information associated with a reproducible portion of a computer program is injected into a network by a node, a commutative error detection value is calculated. At intervals, node fault detection apparatus associated with the multiple node computer system retrieve commutative error detection values associated with the node and stores them in memory. When the computer program is executed again by the multiple node computer system, new commutative error detection values are created and stored in memory. The node fault detection apparatus identifies faulty nodes by comparing commutative error detection values associated with reproducible portions of the application program generated by a particular node from different runs of the application program. Differences in values indicate a possible faulty node.

US Patent:

7418068, Aug 26, 2008

Filed:

Feb 25, 2002

Appl. No.:

10/468992

Inventors:

Wayne Melvin Barrett - Rochester MN, US
Dong Chen - Croton On Hudson NY, US
Paul William Coteus - Yorktwon Heights NY, US
Alan Gene Gara - Mount Kisco NY, US
Rory Jackson - Eastchester NY, US
Gerard Vincent Kopcsay - Yorktown Hieghts NY, US
Ben Jesse Nathanson - Teaneck NY, US
Paylos Michael Vranas - Bedford Hills NY, US
Todd E. Takken - Brewster NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 7/00

US Classification:

375355, 713400

Abstract:

A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.

US Patent:

7444385, Oct 28, 2008

Filed:

Feb 25, 2002

Appl. No.:

10/468997

Inventors:

Matthias A. Blumrich - Ridgefield CT, US
Dong Chen - Croton-On-Hudson NY, US
Paul W. Coteus - Yorktown Heights NY, US
Alan G. Gara - Mount Kisco NY, US
Mark E Giampapa - Irvington NY, US
Philip Heidelberger - Cortlandt Manor NY, US
Gerard V. Kopcsay - Yorktown Heights NY, US
Todd E. Takken - Mount Kisco NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/16

US Classification:

709217, 709224, 710260

Abstract:

A system and method for generating global asynchronous signals in a computing structure. Particularly, a global interrupt and barrier network is implemented that implements logic for generating global interrupt and barrier signals for controlling global asynchronous operations performed by processing elements at selected processing nodes of a computing structure in accordance with a processing algorithm; and includes the physical interconnecting of the processing nodes for communicating the global interrupt and barrier signals to the elements via low-latency paths. The global asynchronous signals respectively initiate interrupt and barrier operations at the processing nodes at times selected for optimizing performance of the processing algorithms. In one embodiment, the global interrupt and barrier network is implemented in a scalable, massively parallel supercomputing device structure comprising a plurality of processing nodes interconnected by multiple independent networks, with each node including one or more processing elements for performing computation or communication activity as required when performing parallel algorithm operations. One multiple independent network includes a global tree network for enabling high-speed global tree communications among global tree network nodes or sub-trees thereof.

US Patent:

7529895, May 5, 2009

Filed:

Dec 28, 2006

Appl. No.:

11/617276

Inventors:

Matthias A. Blumrich - Ridgefield CT, US
Dong Chen - Croton On Hudson NY, US
Paul W. Coteus - Yorktown Heights NY, US
Alan G. Gara - Mount Kisco NY, US
Mark E. Giampapa - Irvington NY, US
Philip Heidelberger - Cortlandt Manor NY, US
Dirk Hoenicke - Ossining NY, US
Martin Ohmacht - Brewster NY, US
Todd E. Takken - Mount Kisco NY, US
Pavlos M. Vranas - Bedford Hills NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/28

US Classification:

711151, 711158, 711213

Abstract:

A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple perfecting for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefect rather than some other predictive algorithm.