Timothy C Krywanczyk

US Patent:

6340601, Jan 22, 2002

Filed:

Dec 30, 1999

Appl. No.:

09/476237

Inventors:

Timothy C. Krywanczyk - Essex Junction VT
Michael S. Lube - Richmond VT
Matthew D. Moon - Jeffersonville VT
Rock Nadeau - Jericho VT
Clark D. Reynolds - Colchester VT
Dean A. Schaffer - Essex Junction VT
Joel M. Sharrow - South Hero VT
David C. Thomas - Richmond VT
Eric J. White - Charlotte VT
Kenneth H. Yao - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 214763

US Classification:

438 4, 438626, 438633, 438645

Abstract:

A method of reworking copper metallurgy on semiconductor devices which includes selective removal of insulator, selective removal of copper, non-selective removal of copper and insulator followed by the redeposition of an insulating copper barrier layer and at least one metallurgical interconnect layer.

US Patent:

6355565, Mar 12, 2002

Filed:

Jul 12, 2001

Appl. No.:

09/904323

Inventors:

Paul M. Feeney - Richmond VT
Timothy C. Krywanczyk - Essex Junction VT
Lawrence D. David - Dover NH
Matthew T. Tiersch - Essex Junction VT
Eric J. White - Charlotte VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2100

US Classification:

438691, 438692, 438693

Abstract:

A ferric nitrate-alumina based slurry useful for Chemical-Mechanical-Polishing of tungsten metallurgy and silica based oxides on semiconductor substrates in which the suspension and stability of abrasive material in the slurry is essentially stable. The slurry formulation is balanced to provide low residue of foreign material after polishing and due to its reduced ferric nitrate concentration will be less corrosive than prior art slurries. The recipe for the slurry includes of a 30% wt silica suspension, about 800 ml of 40% by wt ferric nonahydrate, liters and enough 70% wt nitric acid to adjust the pH of the slurry to about 1. 2 to 1. 4.

US Patent:

6455434, Sep 24, 2002

Filed:

Oct 23, 2001

Appl. No.:

10/001562

Inventors:

Chad R. Binkerd - Burlington VT
Jose L. Cruz - Essex Junction VT
Timothy C. Krywanczyk - Essex Junction VT
Brian D. Pfeifer - Milton VT
Rosemary A. Previti-Kelly - Burlington VT
Patricia Schink - Burlington VT
Amye L. Wells - Underhill VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21302

US Classification:

438692, 438633, 438631

Abstract:

The present invention provides a method of preventing the build-up of polishing material within low areas of a substrate during polishing. Following the blanket deposition of a first layer, a selectively removable material is deposited over the first layer, wherein the selectively removable material fills the low areas. A surface of the substrate is polished removing the excess first layer and selectively removable material from the surface, leaving the first layer and selectively removable material within the low area. Following polishing, the selectively removable material is removed from the low areas prior to the deposition of a second layer.

US Patent:

6599173, Jul 29, 2003

Filed:

Jun 30, 2000

Appl. No.:

09/608941

Inventors:

Jose L. Cruz - Essex Junction VT
Cuc K. Huynh - Jericho VT
Timothy C. Krywanczyk - Essex Junction VT
Douglas K. Sturtevant - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B24B 722

US Classification:

451 41, 451 57

Abstract:

A CMP slurry for and method of polishing a semiconductor wafer during formation of metal interconnects are disclosed. The present invention utilizes a first slurry comprising a first oxidizer, preferably ferric nitrate, to remove the excess metal of the metal interconnect but which leaves the metal residues on the surface of the wafer. A second slurry comprising another oxidizer, preferably potassium iodate solution, having a greater affinity to both the metal residue and the liner material than the underlying dielectric is used to remove the metal residue and liner material with significantly reduced scratching of the underlying dielectric. The more robust metal interconnects formed utilizing the present invention is effective in lowering the overall resistance of a wafer, reducing the number of shorts, and provides greater protection of the underlying dielectric. Overpolishing of the wafer and its associated problems are avoided.

US Patent:

6888223, May 3, 2005

Filed:

Apr 1, 2003

Appl. No.:

10/405763

Inventors:

Donald W. Brouillette - St. Albans VT, US
Joseph D. Danaher - Hinesburg VT, US
Timothy C. Krywanczyk - Essex Junction VT, US
Amye L. Wells - Underhill VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L023/048

US Classification:

257621, 257622, 438459, 438667

Abstract:

A structure and method of formation. The substrate has front and back surfaces on opposite sides of the substrate. The substrate has a backside portion extending from the back surface to a second depth into the substrate as measured from the front surface. At least one via is formed in the substrate and extends from the front surface to a via depth into the substrate. The via depth is specific to each via. The via depth of each via is less than an initial thickness of the substrate. The second depth does not exceed the minimum via depth of the via depths. Organic material (e. g. , photoresist) is inserted into each via. The organic material is subsequently covered with a tape, followed by removal of the backside portion of the substrate. The tape is subsequently removed from the organic material, followed by removal of the organic material from each via.

US Patent:

7025891, Apr 11, 2006

Filed:

Aug 29, 2003

Appl. No.:

10/604991

Inventors:

Steven R. Codding - Underhill Center VT, US
Timothy C. Krywanczyk - Essex Junction VT, US
Joseph D. Danaher - Hinesburg VT, US
John C. Malinowski - Jericho VT, US
James R. Palmer - Hinesburg VT, US
Melvin T. Kelly - Starksboro VT, US
Caitlin W. Weinstein - Cambridge MA, US
Wolfgang Sauter - Richmond MA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B44C 1/22
C25F 3/00

US Classification:

216 12

Abstract:

A method of treating a molybdenum (moly) mask used in a C4 process to pattern C4 contacts. The moly mask has a wafer side which contacts a wafer during the C4 process and has a rough surface that includes spikes/projections of moly. The moly mask also has a non wafer side and a plurality of holes extending through the mask to pattern C4 contacts in the C4 process. An adhesive layer, such as an adhesive tape, is applied to the non wafer side of the moly mask, to enable a polishing tool to pull a vacuum on the non wafer side of the moly mask in spite of the presence of the holes to secure the moly mask during a subsequent polishing step. The tape also functions as a cushion so that defects on the non wafer side of the moly mask do not replicate through the moly mask to the polished wafer side of the moly mask. The wafer side of the moly mask is then subjected to mechanical or chemical/mechanical polishing to substantially remove the spikes of moly without significantly altering the dimensions of the moly mask or the holes.

US Patent:

7074715, Jul 11, 2006

Filed:

Nov 15, 2004

Appl. No.:

10/989059

Inventors:

Donald W. Brouillette - St. Albans VT, US
Joseph D. Danaher - Hinesburg VT, US
Timothy C. Krywanczyk - Essex Junction VT, US
Amye L. Wells - Underhill VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/4763

US Classification:

438637, 438638, 438640

Abstract:

A structure and method of formation. The substrate has front and back surfaces on opposite sides of the substrate. The substrate has a backside portion extending from the back surface to a second depth into the substrate as measured from the front surface. At least one via is formed in the substrate and extends from the front surface to a via depth into the substrate. The via depth is specific to each via. The via depth of each via is less than an initial thickness of the substrate. The second depth does not exceed the minimum via depth of the via depths. Organic material (e. g. , photoresist) is inserted into each via. The organic material is subsequently covered with a tape, followed by removal of the backside portion of the substrate. The tape is subsequently removed from the organic material, followed by removal of the organic material from each via.

US Patent:

7135124, Nov 14, 2006

Filed:

Nov 13, 2003

Appl. No.:

10/713659

Inventors:

Timothy C. Krywanczyk - Essex Junction VT, US
Edmund J. Sprogis - Underhill VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/302
C23F 1/00
B24B 1/00

US Classification:

216 88, 216 89, 438692, 438693, 451 57

Abstract:

In accordance with the foregoing objects and advantages, the present invention provides a fabrication device that may be used during the grinding operation of the fabrication process. The fabrication device comprises a socket plate that includes a plurality of cavities formed therein that correspond in position and number to the solder (or other conductive material) bumps formed on the front surface of a product wafer.