Thomas J Thomas

US Patent:

6538497, Mar 25, 2003

Filed:

Mar 27, 2001

Appl. No.:

09/819135

Inventors:

Thomas P. Thomas - Hillsboro OR
Ian A. Young - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G05F 156

US Classification:

327543, 327541, 307 44, 323313

Abstract:

A method and apparatus for maintaining a stable power supply voltage. The method comprises using a power supply to provide power at a power supply voltage to a plurality of semiconductor devices. The power supply voltage is nominally at an optimal power supply voltage. A fast increase in the current can cause a drop in the supply voltage, since the high rate of change in current is through the package inductance. The power supply voltage is monitored. Further, a supplemental higher voltage power supply is used to boost the power supply voltage to substantially the optimal power supply voltage if the power supply voltage decreases by a threshold value.

US Patent:

6650161, Nov 18, 2003

Filed:

Dec 28, 2000

Appl. No.:

09/751942

Inventors:

Thomas P. Thomas - Hillsboro OR
Ian A. Young - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 300

US Classification:

327291, 327551, 327293

Abstract:

A clock distribution network for an integrated circuit is disclosed. The network includes a plurality of inverters that distribute a clock signal. The inverters are powered by a power supply. The power supply is supplied to the inverters through a source follower transistor that has its gate connected to a regulated DC voltage. The source follower transistor operates in the saturation region.

US Patent:

6741102, May 25, 2004

Filed:

Apr 26, 1999

Appl. No.:

09/300757

Inventors:

Thomas P. Thomas - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03L 7089

US Classification:

327 3, 327 12

Abstract:

Briefly, in accordance with one embodiment, an integrated circuit includes a phase-frequency detector (PFD) including two clock input ports, an up signal port and a down signal port. The PFD includes digital circuitry including transistors coupled in a configuration to adjust an amount of overlap of an up output signal pulse and a down output signal pulse based, at least in part, upon the magnitude of an amount of phase delay between two respective clock signal pulses applied to the two input ports. Of course, additional embodiments are also disclosed.

US Patent:

6760801, Jul 6, 2004

Filed:

Mar 6, 2001

Appl. No.:

09/801028

Inventors:

Thomas P. Thomas - Hillsboro OR
Ian A. Young - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1314

US Classification:

710305, 710100, 375257, 375377

Abstract:

A multi-drop bus input/output method and apparatus is disclosed. The apparatus comprises a multi-drop bus that has termination ends. The multi-drop bus also has a characteristic impedance. The multi-drop bus can be used for communication between devices. Devices that are attached to a termination end of the bus drive data onto the bus at the characteristic impedance. Devices that are attached to the bus, but not the termination ends, drive data onto the bus at one-half of the characteristic impedance. An end device terminates to ground with the characteristic impedance, and middle devices have high impedance, when not driving data.

US Patent:

6856129, Feb 15, 2005

Filed:

Jul 9, 2002

Appl. No.:

10/190712

Inventors:

Thomas P. Thomas - Beaverton OR, US
Douglas N. Stunkard - Portland OR, US
Miriam R. Reshotko - Portland OR, US
Brandon C. Barnett - Beaverton OR, US
Ian A. Young - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R031/00

US Classification:

3241581, 324765, 324767

Abstract:

A measurement system is provided that includes a probe device having an integrated amplifier. The integrated amplifier may be a transimpedence amplifier that amplifies input current to an output voltage.

US Patent:

7724078, May 25, 2010

Filed:

Mar 22, 2007

Appl. No.:

11/726788

Inventors:

Nasser A. Kurd - Portland OR, US
Chaodan Deng - Portland OR, US
Thomas P. Thomas - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G05F 1/10

US Classification:

327544, 331185, 331186

Abstract:

A processing device includes a Phase Locked Loop (PLL) system with an adjustable power supply designed to track the power supply provided to one or more of the cores in the processor device. The PLL no longer operates at a fixed voltage level that is held constant and independent from the requested core frequency or the core digital voltage, but rather the power supply to the phase locked loop is adjusted along with the main power supply to the processor core.

US Patent:

20130300475, Nov 14, 2013

Filed:

Dec 22, 2011

Appl. No.:

13/994808

Inventors:

Nasser A. Kurd - Portland OR, US
Thomas P. Thomas - Beaverton OR, US

International Classification:

H03L 7/22

US Classification:

327158

Abstract:

Low power, jitter and latency clocking with common reference clock signals for on-package input/output interfaces. A filter phase locked loop circuit in a master device on a first die provides a clock signal having a frequency of 2F. A local phase locked loop circuit in the master device on the first die is coupled with the filter phase locked loop to provide a clock signal to functional components of the master device through a local clock divider circuit to provide a clock signal of F to the functional components. A remote phase locked loop circuit in a slave device on a second die is coupled with the filter phase locked loop to provide a clock signal to one or more functional components of the slave device through a local clock divider circuit to provide a clock signal of F to the functional components.

US Patent:

20130318266, Nov 28, 2013

Filed:

Dec 22, 2011

Appl. No.:

13/995007

Inventors:

Thomas P. Thomas - Beaverton OR, US
Rajesh Kumar - Portland OR, US

International Classification:

G06F 13/42

US Classification:

710106

Abstract:

An on-package interface. A first set of single-ended transmitter circuits on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits on a second die. The receiver circuits have no termination and no equalization. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.