Thomas B Gorczyca

US Patent:

6368410, Apr 9, 2002

Filed:

Jun 28, 1999

Appl. No.:

09/340793

Inventors:

Thomas Bert Gorczyca - Schenectady NY
Udo Heinz Retzlaff - Schwarzenbek, DE
Stephan Popp - Hamburg, DE

Assignee:

General Electric Company - Schenectady NY

International Classification:

C23C 1600

US Classification:

118715, 118500

Abstract:

A semiconductor processing article is characterized by extended useful life. The article is used in a semiconductor furnace system, particularly in a low pressure chemical vapor deposition furnace for prolonged periods without requiring cleaning to remove build-up film. The semiconductor processing article is a quartz body characterized by a surface roughness having a first component with an average deviation from a first mean surface of about 2. 5 to 50 microns, and a second component with an average deviation from a second mean surface of about 0. 25 to 5 microns. The processing article is prepared for use in the furnace by mechanically blasting and chemically etching the surface of the article.

US Patent:

6396153, May 28, 2002

Filed:

Jan 25, 2001

Appl. No.:

09/768598

Inventors:

Raymond Albert Fillion - Niskayuna NY
Ernest Wayne Balch - Ballston Spa NY
Ronald Frank Kolc - Cherry Hill NJ
Robert John Wojnarowski - Ballston Lake NY
Leonard Richard Douglas - Burnt Hills NY
Thomas Bert Gorczyca - Schenectady NY

Assignee:

General Electric Company - Schenectady NY

International Classification:

H01L 2348

US Classification:

257774, 257773

Abstract:

One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad. In related embodiments vias are pre-metallized and coupled to chip pads of the circuit chips by an electrically conductive binder. Thin film passive components and multilayer interconnections can additionally be incorporated into the package.

US Patent:

6504233, Jan 7, 2003

Filed:

Jun 28, 1999

Appl. No.:

09/340794

Inventors:

Thomas Bert Gorczyca - Schenectady NY
Margaret Ellen Lazzeri - Schenectady NY
Frederic Francis Ahlgren - Highland Heights OH

Assignee:

General Electric Company - Niskayuna NY

International Classification:

H01L 2358

US Classification:

257629, 257632, 257647, 428426, 428428, 428446, 4285428, 118 70

Abstract:

A semiconductor processing component includes a quartz body characterized by silicon oxide filled micro cracks. The component is utilized as a processing component in a semiconductor furnace system. The quartz body is prepared by cleaning the component to remove a build up silicon layer and to expose micro cracks in the surface of the component and to etch the micro cracks into trenches. A silicon layer is applied onto the processing component body and at least a portion of the silicon is oxidized to silica to fill the trenches in the surface of the component body.

US Patent:

6508961, Jan 21, 2003

Filed:

Aug 4, 2000

Appl. No.:

09/633141

Inventors:

Thomas Paul Feist - Clifton Park NY
Thomas Bert Gorczyca - Schenectady NY

Assignee:

General Electric Company - Niskayuna NY

International Classification:

B29D 1100

US Classification:

264 133, 2491141, 249134, 249135, 26432016, 425810, 427135

Abstract:

A method for molding an optical disk includes applying a thermally insulative mold insert onto a thermally conductive mold form by coating the mold insert on the mold form. The mold insert has a coefficient of thermal expansion compatible with the coefficient of thermal expansion of the mold form and includes an adhesion promoting material. The method further includes positioning the coated mold form in a thermally conductive mold apparatus with the mold insert positioned between the mold form and the mold apparatus; injecting a molten thermoplastic material into the mold apparatus; retaining the molten thermoplastic material in the mold apparatus for a time sufficient for the molten thermoplastic material to cool below its glass transition temperature to form the optical disk; and ejecting the optical disk from the mold apparatus.

US Patent:

6533968, Mar 18, 2003

Filed:

Sep 5, 2000

Appl. No.:

09/655322

Inventors:

Thomas Paul Feist - Clifton Park NY
Thomas Bert Gorczyca - Schenectady NY

Assignee:

General Electric Company - Niskayuna NY

International Classification:

B29D 1100

US Classification:

264 133, 264 21, 264 81, 264219, 264334, 264338

Abstract:

A method for molding an optical disk comprises: applying a thermally insulative insert coating to at least one thermally insulative mold insert to provide at least one coated mold insert having a reduced surface roughness; positioning the coated mold insert between a thermally conductive mold form and a portion of a thermally conductive mold apparatus; injecting a molten thermoplastic material into the mold apparatus; retaining the material in the mold apparatus for a time sufficient for the molten thermoplastic material to cool below its glass transition temperature to form the optical disk; and ejecting the optical disk from the mold apparatus. In another embodiment, the mold insert is coated or laminated on the mold form with the mold insert having a coefficient of thermal expansion compatible with the coefficient of thermal expansion of the mold form. In another embodiment, the mold insert is fabricated by being applied, cured, and then removed from a release layer.

US Patent:

6548189, Apr 15, 2003

Filed:

Oct 26, 2001

Appl. No.:

09/682871

Inventors:

Somasundaram Gunasekaran - Bangalore, IN
Thomas Bert Gorczyca - Schenectady NY
Herbert Stanley Cole - Burnt Hills NY

Assignee:

General Electric Company - Schenectady NY

International Classification:

B32B 1508

US Classification:

428626, 257793, 428414, 428620, 523466, 525524, 525533, 528 94, 528112

Abstract:

In the present invention an adhesive composition is provided. The adhesive composition includes epoxidized cashew nutshell liquid, a catalyst, and diglycidyl ether of bisphenol A. The invention may further include at least one additive selected from the group including curing agents, bonding enhancers, hardeners, flexibilizers, tackifiers, and mixtures thereof.

US Patent:

6602739, Aug 5, 2003

Filed:

Mar 19, 2002

Appl. No.:

10/101231

Inventors:

James Wilson Rose - Guilderland NY
Thomas Bert Gorczyca - Schenectady NY
Christopher James Kapusta - Duanesburg NY
Ernest Wayne Balch - Ballston Spa NY
Kevin Matthew Durocher - Waterford NY

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

H01L 2144

US Classification:

438126, 438106, 438109, 438125

Abstract:

A method for making a multichip âHDIâ module includes the step of making a substrate for supporting the semiconductor or solid-state chips (or other components) by applying electrical conductor in a pattern to a first dielectric sheet, and applying encapsulating material to the electrical conductor. Apertures are made in the first dielectric sheet and encapsulant at locations at which the chips (or other components) are to be located. The components are affixed to a second dielectric sheet at locations registered with the apertures in the first sheet, and the sheets are juxtaposed with the chips extending into the apertures. This results in the formation of gaps between the components and the edges of the apertures, which gaps are then filled with hardenable or curable material. Electrical connection is made to the pads of the chips by means of a multilayer structure of dielectric sheets with conductor patterns, interconnected by means of plated-through vias.

US Patent:

6706205, Mar 16, 2004

Filed:

Feb 7, 2002

Appl. No.:

10/067380

Inventors:

Thomas Bert Gorczyca - Schenectady NY
Udo Heinz Retzlaff - Schwarzenbek, DE
Stephan Popp - Hamburg, DE

Assignee:

General Electric Company - Niskayuna NY

International Classification:

B24B 100

US Classification:

216 53, 216 52, 216 83, 216 97, 216 99, 451 38, 451 41

Abstract:

A semiconductor processing article is characterized by extended useful life. The article is used in a semiconductor furnace system, particularly in a low pressure chemical vapor deposition furnace for prolonged periods without requiring cleaning to remove build-up film. The semiconductor processing article is a quartz body characterized by a surface roughness having a first component with an average deviation from a first mean surface of about 2. 5 to 50 microns, and a second component with an average deviation from a second mean surface of about 0. 25 to 5 microns. The processing article is prepared for use in the furnace by mechanically blasting and chemically etching the surface of the article.