Theodore J Letavic

US Patent:

6346451, Feb 12, 2002

Filed:

Jun 30, 1999

Appl. No.:

09/343912

Inventors:

Mark Simpson - Ossining NY
Theodore Letavic - Putnam Valley NY

Assignee:

Philips Electronics North America Corporation - New York NY

International Classification:

H01L 21331

US Classification:

438311, 438186, 257134, 257138, 257139, 257285, 257287, 257488

Abstract:

A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral transistor device in an SOI layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first. A lateral drift region of a first conductivity type is provided adjacent the body region, and a drain region of the first conductivity type is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being at least substantially insulated from the body region and drift region by an insulation region. In order to provide improved breakdown voltage characteristics, a dielectric layer is provided over at least a part of the insulation region and the gate electrode, and a field plate electrode is provided over at least a part of the dielectric layer which is in direct contact with the insulation region, with the field plate electrode being connected to an electrode of the lateral transistor device.

US Patent:

6468878, Oct 22, 2002

Filed:

Feb 27, 2001

Appl. No.:

09/794562

Inventors:

John Petruzzello - Carmel NY
Theodore James Letavic - Putnam Valley NY
Mark Simpson - White Plains NY

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

H01L 2176

US Classification:

438454, 438311, 438153, 438154, 438163

Abstract:

An improved method and structure for a transistor device with a lateral drift region and a conducting top field plate is presented. The method consists of decreasing the gate to drain capacitance by means of decreasing the portion of the field plate that is connected to the gate electrode, and hence the effective overlap of the gate with the drift region and drain. This results in decreased energy dissipation in switching the transistor, and more efficient operation. The rate of decrease of the gate to drain capacitance is even faster at higher drain voltages, inuring in significant energy efficiencies in high voltage applications.

US Patent:

6518814, Feb 11, 2003

Filed:

Dec 28, 1999

Appl. No.:

09/473530

Inventors:

Naveed Majid - Mohegan Lake NY
Theodore Letavic - Putnam Valley NY

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

H03L 500

US Classification:

327306, 327334, 327530, 327565

Abstract:

A high-voltage capacitive voltage divider circuit includes a high-voltage Silicon-On-Insulator (SOI) capacitor connected between a high-voltage terminal and a low-voltage terminal, and a low-voltage SOI capacitor connected between the low-voltage terminal and a common terminal. The voltage divider circuit also includes control circuitry for processing a signal generated at the low-voltage terminal in order to provide voltage-related control of a larger circuit employing the voltage divider circuit. The high-voltage SOI capacitor can include an oxide layer on a substrate, with a thinned drift region on the oxide layer, a thick oxide layer over the thinned drift region, and an electrode layer over the thick oxide layer, with the electrode layer and the thinned drift region forming capacitor plates insulated from each other by the thick oxide layer. The capacitive voltage divider circuit may advantageously form part of a Switched Mode Power Supply (SMPS), in which the high-voltage terminal is an output of a diode bridge rectifier of the SMPS, and a comparator is used to sense a stepped-down voltage at the low-voltage terminal and uses this stepped-down voltage to detect an under-voltage condition in the SMPS.

US Patent:

6627958, Sep 30, 2003

Filed:

Dec 10, 2001

Appl. No.:

10/015641

Inventors:

Theodore J. Letavic - Putnam Valley NY
John Petruzzello - Carmel NY

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

H01L 2978

US Classification:

257367, 257347

Abstract:

A lateral high voltage semiconductor device having a sense terminal and a method for sensing a drain voltage of the same are provided. Specifically, the present invention relates to a thin layer, high voltage, lateral silicon-on-insulator (SOI) device having a field plate terminal that is disconnected from a source terminal. By measuring voltage or current on the separate field plate terminal, the drain voltage of the device can be sensed. This sensing capability is a protection scheme against overstress voltage conditions.

US Patent:

6661059, Dec 9, 2003

Filed:

Sep 30, 2002

Appl. No.:

10/261254

Inventors:

Theodore Letavic - Putnam Valley NY
John Petruzzello - Carmel NY
Benoit Dufort - Valhalla NY

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

H01L 2976

US Classification:

257347, 257344, 257408, 438149, 438479, 438517

Abstract:

A lateral insulated gate bipolar PMOS device includes a semiconductor substrate, a buried insulating layer and a lateral PMOS transistor device in an SOI layer on the buried insulating layer having a source region of p-type conductivity. A lateral drift region of n-type conductivity is provided adjacent the body region, and a drain region of the p-type conductivity is provided laterally spaced from the body region by the drift region. An n-type conductivity drain region is formed of a shallow n-type contact surface region inserted into a p-inversion buffer. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being insulated from the body region and drift region by an insulation region.

US Patent:

6717214, Apr 6, 2004

Filed:

May 21, 2002

Appl. No.:

10/152235

Inventors:

Benoit Dufort - Valhalla NY
Theodore Letavic - Putnam Valley NY

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

H01L 2701

US Classification:

257347, 257507

Abstract:

The present invention provides a semiconductor device of the SOI-LDMOS type in which the field plate is divided into a plurality of electrically isolated sub-field plates. At least two of the divided sub-field plates are connected to external circuits for reading their respective output voltages. By connecting a first external circuit and a second external circuit having specific components, one is configured for determining an instantaneous output voltage and the other is configured for determining a change in output voltage as a function of time. Power is disconnected from the semiconductor device if either the instantaneous voltage or the derivative of voltage over time exceeds an established value.

US Patent:

6794719, Sep 21, 2004

Filed:

Jun 28, 2001

Appl. No.:

09/894083

Inventors:

John Petruzzello - Carmel NY
Theodore James Letavic - Putnam Valley NY
Mark Simpson - White Plains NY

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

H01L 2184

US Classification:

257350, 257347, 257335, 257409, 257647

Abstract:

A hybrid semiconductor device is presented in which one or more diode regions are integrated into a transistor region. In a preferred embodiment the transistor region is a continuous (self-terminating) SOI LDMOS device in which are integrated one or more diode portions. Within the diode portions, since there is only one PN junction, the mechanism for breakdown failure due to bipolar turn-on is nonexistent. The diode regions are formed such that they have a lower breakdown voltage than the transistor region, and thus any transient voltage (or current) induced breakdown is necessarily contained in the diode regions. In a preferred embodiment, the breakdown voltage of the diode portions is lowered by narrowing their field plate length relative to the transistor portion of the device. This allows the device to survive any such breakdown without being destroyed, resulting in a more rugged and more reliable device.

US Patent:

6833726, Dec 21, 2004

Filed:

Feb 13, 2004

Appl. No.:

10/779093

Inventors:

John Petruzzello - Carmel NY
Benoit Dufort - Valhalla NY
Theodore Letavic - Putnam Valley NY

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G01R 3126

US Classification:

324765, 324522

Abstract:

The present invention provides a semiconductor device of the SOI-LDMOS type in which the field plate is divided into a plurality of electrically isolated sub-field plates. At least two of the divided sub-field plates are connected to external circuits for reading their respective output voltages. By connecting a first external circuit and a second external circuit having specific components, one is configured for determining an instantaneous output voltage and the other is configured for determining a change in output voltage as a function of time. Power is disconnected from the semiconductor device if either the instantaneous voltage or the derivative of voltage over time exceeds an established value.