Avago Technologies - Fort Collins since Dec 2011
Fabrication Engineer, Reticle Services
STMicroelectronics - Longmont, Colorado Sep 2010 - Aug 2011
Hardware Design Engineer
Avago Technologies Dec 1999 - Jan 2009
Expert ASIC Design Engineer
Agilent Technologies May 2000 - Jul 2005
IC Design Engineer
HP Dec 1999 - May 2000
IC Design Engineer
Education:
University of Illinois at Urbana-Champaign 1991
Master of Science, Electrical Engineering
Iowa State University 1984
Bachelor of Science, Computer Engineering
Sylvia Patterson - Fort Collins CO, US Robert Zimmer - Loveland CO, US
International Classification:
G06F 17/50
US Classification:
703014000
Abstract:
A method and apparatus is presented for performing simulation of complex circuits. A circuit is simulated in a fast simulator. State information, which is the output of the fast simulator, is translated in a translator and then the circuit is simulated in a slow simulator. In one embodiment, the circuit is modeled in a digital format in the fast simulator and modeled in an analog format in the slow simulator.
Serdes Cooperates With The Boundary Scan Test Technique
Sylvia Patterson - Ft Collins CO Jeff Rearick - Ft Collins CO
Assignee:
Agilent Technologies, Inc. - Palo Alto CA
International Classification:
H03M 1300
US Classification:
341100, 341 55, 341 58, 324765, 714729
Abstract:
Improvement in the transmission of Boundary Scan Test mode data may be achieved through the assignment of boundary scan test mode traffic to selected bit patterns that facilitate clock recovery and frame alignment in the serial channel. The encoding of boundary scan test traffic as such may be achieved through either multiplexed transmission to the serializer/deserializer (SERDES) alongside a regular channel encoder or incorporated into the channel encoder.
Clarence Estes, Eva Tavares, Mattt Lawson, Melissa Basaldua, Julie Brown, Elizabeth Massiwer, Amber Funkhouser, Jose Garcia, Tiunna Wilson, Erik Rio, Aj Swint, Marcus Hubert