Suzette Keefe Pangrle

US Patent:

6352930, Mar 5, 2002

Filed:

Mar 22, 2001

Appl. No.:

09/814636

Inventors:

Kathleen R. Early - Santa Clara CA
Suzette K. Pangrle - Cupertino CA
Maria C. Chan - San Jose CA
Lewis Shen - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21302

US Classification:

438694, 428698, 438584, 438585, 438 72, 438717, 438736

Abstract:

In the manufacture of sub-0. 35 micron semiconductors using deep ultraviolet lithography, a bilayer of silicon dioxide on top of silicon oxynitride is used as bottom anti-reflective coating and an etch hard mask for photolithographic resist. Since the silicon dioxide is optically transparent at the deep ultraviolet wavelengths being used (248 nm), its thickness in combination with a preselected reflective silicon oxynitride thickness satisfies the zero reflectivity goal and, at the same time, is adequately thick to serve as a hard mask for self-aligned etch and self-aligned-source etch.

US Patent:

6361837, Mar 26, 2002

Filed:

Jan 15, 1999

Appl. No.:

09/232359

Inventors:

Suzette K. Pangrle - Cupertino CA
Richard J. Huang - Cupertino CA
Shekhar Pramanick - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

B05D 306

US Classification:

427552, 427533, 427504, 427503, 427526, 438781, 438788, 438792

Abstract:

The invention provides a system and a method for densifying a surface of a porous film. By reducing the porosity of a film, the method yields a densified film that is more impenetrable to subsequent liquid processes. The method comprises the steps of providing a film having an exposed surface. The film can be supported by a semiconductor substrate. When the film is moved to a processing position, a focused source of radiation is created by a beam source. The exposed surface of the film is then irradiated by the beam source at the processing position until a predetermined dielectric constant is achieved. The film or beam source may be rotated, inclined, and/or moved between a variety of positions to ensure that the exposed surface of the film is irradiated evenly.

US Patent:

6380067, Apr 30, 2002

Filed:

May 31, 2000

Appl. No.:

09/588119

Inventors:

Ramkumar Subramanian - San Jose CA
Minh Van Ngo - Fremont CA
Suzette K. Pangrle - Cupertino CA
Kashmir Sahota - Fremont CA
Christopher F. Lyons - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21302

US Classification:

438624, 438622, 438740, 438723, 438724, 430 5

Abstract:

The present invention provides a method for manufacturing a semiconductor device with a bottom anti-reflective coating (BARC) that acts as an etch stop layer and does not need to be removed. In one embodiment, electrical devices are formed on a semiconductor substrate. Contacts are then formed for each electrical device and a partially UV transparent BARC is then deposited. An inter-layer dielectric (ILD) layer is then formed and then covered with photoresist. A top ARC (TARC) is then added and the photoresist is then photolithographically processed and subsequently developed. The TARC, ILD, and BARC layers are then selectively etched down to the device contacts forming local interconnects. The photoresist and TARC are later removed, but the BARC does not require removal due to its optical transparency.

US Patent:

6383950, May 7, 2002

Filed:

Oct 10, 2001

Appl. No.:

09/974568

Inventors:

Suzette K. Pangrle - Cupertino CA
Minh Van Ngo - Fremont CA
Susan Tovar - Gilroy CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21469

US Classification:

438778, 438393, 438255, 438396, 438486, 438665

Abstract:

An insulating and capping structure of an integrated circuit is formed on a semiconductor wafer. An insulating layer is formed on the semiconductor wafer, and the insulating layer is comprised of a dielectric material having a low dielectric constant that is less than about 4. 0 and having chemical bonds that are chemically reactive with a predetermined reactant. A reaction barrier layer is formed on the insulating layer, and the reaction barrier layer is comprised of a material that is not chemically reactive with the predetermined reactant. A capping layer is formed on the reaction barrier layer, and the capping layer is formed using the predetermined reactant. The reaction barrier layer prevents contact of the predetermined reactant with the insulating layer to prevent reaction of the predetermined reactant with the chemical bonds of the dielectric material of the insulating layer that are chemically reactive with the predetermined reactant such that the low dielectric constant of the dielectric material of the insulating layer is not increased by the formation of the capping layer. The present invention may be used to particular advantage when the predetermined reactant used for forming the capping layer and that is reactive with the insulating layer is oxygen plasma and when the reaction barrier layer is comprised of silicon nitride.

US Patent:

6462417, Oct 8, 2002

Filed:

Jan 29, 2001

Appl. No.:

09/772750

Inventors:

Pin-Chin Connie Wang - Menlo Park CA
Amit P. Marathe - Milpitas CA
Minh Van Ngo - Fremont CA
Suzette K. Pangrle - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2348

US Classification:

257753, 257758, 257762, 257763, 257765

Abstract:

An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, an alloy-barrier layer lining the channel opening, and a conductor core filling the channel opening. An alloy layer is deposited which contains an element capable of reacting during thermal treatment with both the conductor core and the channel dielectric layer to form an alloy-barrier to diffusion of the material of the conductor core to the channel dielectric layer. The alloy-barrier layer is reacted with the conductor core and the channel dielectric layer to form a compound which provides a bond which blocks surface diffusion and permits conductor core to conductor core diffusion in dual inlaid integrated circuits.

US Patent:

6468894, Oct 22, 2002

Filed:

Mar 21, 2001

Appl. No.:

09/813309

Inventors:

Kai Yang - San Jose CA
Suzette K. Pangrle - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2348

US Classification:

438622, 438253, 438644, 438678, 438685

Abstract:

A metal interconnect structure and method of making the same provides a low k dielectric layer on a substrate that contains the first metal line. A plurality of vias are formed in the low k dielectric layer, along with a second metal line. A first set of the plurality of vias are connected between the first and second metal lines, and a second set of the plurality of vias are not connected between the first and second metal lines. The second set of vias form dummy vias that increase the mechanical strength of the via layer and increase the resistance to delamination and scratching during chemical mechanical polishing.

US Patent:

6472336, Oct 29, 2002

Filed:

Feb 23, 2000

Appl. No.:

09/511585

Inventors:

Suzette K. Pangrle - Cupertino CA
Minh Van Ngo - Fremont CA
Richard J. Huang - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2131

US Classification:

438784, 257632

Abstract:

Insulating material is formed to surround interconnect structures of an integrated circuit. A first semiconductor wafer is placed in a reaction chamber for forming the insulating material surrounding the interconnect structures of the integrated circuit on the first semiconductor wafer. A corrosive dielectric material having low dielectric constant is deposited to surround the interconnect structures, and the corrosive dielectric material fills any gaps between the interconnect structures. Deposition of the corrosive dielectric material is performed within the reaction chamber, and the corrosive dielectric material is deposited on the reaction chamber during deposition of the corrosive dielectric material on the first semiconductor wafer. An encapsulating layer is formed over the corrosive dielectric material on the first semiconductor wafer and on the reaction chamber to prevent contact of the corrosive dielectric material to any exposed structure of a second semiconductor wafer to be subsequently placed into the reaction chamber when such an exposed structure is reactive with the corrosive dielectric material.

US Patent:

6475929, Nov 5, 2002

Filed:

Feb 1, 2001

Appl. No.:

09/774708

Inventors:

Calvin T. Gabriel - Cupertino CA
Suzette K. Pangrle - Cupertino CA
Lynne A. Okada - Sunnyvale CA
Fei Wang - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2358

US Classification:

438783, 438781, 438586

Abstract:

A method of manufacturing a low-k semiconductor structure including the steps of forming a low-k dielectric layer, forming a sacrificial etch stop layer adjacent the low-k dielectric layer, and applying energy to the sacrificial etch stop layer to diffuse a component of the sacrificial etch stop layer into the adjacent low-k dielectric layer. This diffusion of the component lowers the dielectric constant of the adjacent low-k dielectric layer.