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Suzette K Pangrle

age ~61

from Cupertino, CA

Also known as:
  • Suzette Keefe Pangrle
  • Suzette Pangrle
  • Suzette Dr Pangrle
  • Suzete Pangrle
  • Barry Pangrle
  • Angrie P Suzette
21849 Lindy Ln, Cupertino, CA 95014408-446-4624

Suzette Pangrle Phones & Addresses

  • 21849 Lindy Ln, Cupertino, CA 95014 • 408-446-4624
  • Orange, CA
  • Goleta, CA
  • State College, PA
  • San Jose, CA
  • 21849 Lindy Ln, Cupertino, CA 95014 • 408-623-9474

Work

  • Company:
    Vertical circuits, inc - Scotts Valley, CA
    May 2009
  • Position:
    Principal scientist, advanced process technology lead, technology reliability & fa

Education

  • School / High School:
    University of CA, UCSC
    2012
  • Specialities:
    Project & Program Management Certification (in progress)

Skills

Project Management Device Technology In...

Us Patents

  • Bilayer Anti-Reflective Coating And Etch Hard Mask

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  • US Patent:
    6352930, Mar 5, 2002
  • Filed:
    Mar 22, 2001
  • Appl. No.:
    09/814636
  • Inventors:
    Kathleen R. Early - Santa Clara CA
    Suzette K. Pangrle - Cupertino CA
    Maria C. Chan - San Jose CA
    Lewis Shen - Cupertino CA
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
  • International Classification:
    H01L 21302
  • US Classification:
    438694, 428698, 438584, 438585, 438 72, 438717, 438736
  • Abstract:
    In the manufacture of sub-0. 35 micron semiconductors using deep ultraviolet lithography, a bilayer of silicon dioxide on top of silicon oxynitride is used as bottom anti-reflective coating and an etch hard mask for photolithographic resist. Since the silicon dioxide is optically transparent at the deep ultraviolet wavelengths being used (248 nm), its thickness in combination with a preselected reflective silicon oxynitride thickness satisfies the zero reflectivity goal and, at the same time, is adequately thick to serve as a hard mask for self-aligned etch and self-aligned-source etch.
  • Diode And Resistive Memory Device Structures

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  • US Patent:
    8035099, Oct 11, 2011
  • Filed:
    Feb 27, 2008
  • Appl. No.:
    12/072588
  • Inventors:
    Manuj Rathor - Milpitas CA,
    An Chen - Sunnyvale CA,
    Steven Avanzino - Cupertino CA,
    Suzette K. Pangrle - Cupertino CA,
  • Assignee:
    Spansion LLC - Sunnyvale CA
  • International Classification:
    H01L 29/12
  • US Classification:
    257 43, 257E45003
  • Abstract:
    In an electronic device, a diode and a resistive memory device are connected in series. The diode may take a variety of forms, including oxide or silicon layers, and one of the layers of the diode may make up a layer of the resistive memory device which is in series with that diode.
  • Semiconductor Device Built On Plastic Substrate

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  • US Patent:
    8044387, Oct 25, 2011
  • Filed:
    Jul 7, 2004
  • Appl. No.:
    10/885959
  • Inventors:
    Matthew S. Buynoski - Palo Alto CA,
    Uzodinma Okoroanyanwu - Mountain View CA,
    Suzette K. Pangrle - Cupertino CA,
    Nicholas H. Tripsas - San Jose CA,
  • Assignee:
    Spansion LLC - Sunnyvale CA
  • International Classification:
    H01L 35/24
  • US Classification:
    257 40, 257759, 257E39007
  • Abstract:
    Disclosed are semiconductor memory devices containing a plastic substrate and at least one active device supported by the plastic substrate, the active device containing an organic semiconductor material. The semiconductor memory devices containing a plastic substrate may further contain a polymer dielectric and/or a conductive polymer.
  • Damascene Metal-Insulator-Metal (Mim) Device With Improved Scaleability

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  • US Patent:
    8232175, Jul 31, 2012
  • Filed:
    Sep 14, 2006
  • Appl. No.:
    11/521204
  • Inventors:
    Suzette K. Pangrle - Cupertino CA,
    Steven Avanzino - Cupertino CA,
    Sameer Haddad - San Jose CA,
    Michael VanBuskirk - Saratoga CA,
    Manuj Rathor - Milpitas CA,
    James Xie - San Jose CA,
    Kevin Song - Santa Clara CA,
    Christie Marrian - San Jose CA,
    Bryan Choo - Mountain View CA,
    Fei Wang - San Jose CA,
    Jeffrey A. Shields - Sunnyvale CA,
  • Assignee:
    Spansion LLC - Sunnyvale CA
  • International Classification:
    H01L 21/20
  • US Classification:
    438399, 438396, 257E21006, 257E21008, 257E21009, 257532
  • Abstract:
    A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.
  • Gettering/Stop Layer For Prevention Of Reduction Of Insulating Oxide In Metal-Insulator-Metal Device

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  • US Patent:
    8093698, Jan 10, 2012
  • Filed:
    Dec 5, 2006
  • Appl. No.:
    11/633844
  • Inventors:
    Manuj Rathor - Milpitas CA,
    Matthew Buynoski - Palo Alto CA,
    Joffre F. Bernard - Santa Clara CA,
    Steven Avanzino - Cupertino CA,
    Suzette K. Pangrle - Cupertino CA,
  • Assignee:
    Spansion LLC - Sunnyvale CA
  • International Classification:
    H01G 4/224
  • US Classification:
    257682, 257295, 257E21009, 257E21021, 257E21104, 257E21425, 257E2143, 257E21664
  • Abstract:
    An electronic device includes a first electrode, a second electrode and an insulating layer between the first and second electrodes, which insulating layer may be susceptible to reduction by H. A gettering layer is provided on and in contact with the first electrode, the gettering layer acting as a protective layer for substantially avoiding reduction of the insulating layer by capturing and immobilizing H. A glue layer may be provided between the gettering layer and first electrode. An additional gettering layer may be provided on and in contact with the second electrode, and a glue layer may be provided between the second electrode and additional gettering layer.
  • Metal-Insulator-Metal-Insulator-Metal (Mimim) Memory Device

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  • US Patent:
    8093680, Jan 10, 2012
  • Filed:
    Sep 14, 2006
  • Appl. No.:
    11/521219
  • Inventors:
    Manuj Rathor - Milpitas CA,
    Suzette K. Pangrle - Cupertino CA,
    Steven Avanzino - Cupertino CA,
    Zhida Lan - San Jose CA,
  • Assignee:
    Spansion LLC - Sunnyvale CA
  • International Classification:
    H01L 29/68
  • US Classification:
    257529, 257 30, 257324, 257E2917
  • Abstract:
    The present memory device includes first and second electrodes, first and second insulating layers between the electrodes, the first insulating layer being in contact with the first electrode, the second insulating layer being in contact with the second electrode, and a metal layer between the first and second insulating layers. Further included may be a first oxide layer between and in contact with the first insulating layer and the metal layer, and a second oxide layer between and in contact with the second insulating layer and the metal layer.
  • Damascene Metal-Insulator-Metal (Mim) Device

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  • US Patent:
    8089113, Jan 3, 2012
  • Filed:
    Dec 5, 2006
  • Appl. No.:
    11/633929
  • Inventors:
    Suzette K. Pangrle - Cupertino CA,
    Steven Avanzino - Cupertino CA,
    Sameer Haddad - San Jose CA,
    Michael VanBuskirk - Saratoga CA,
    Manuj Rathor - Milpitas CA,
    James Xie - San Jose CA,
    Kevin Song - Santa Clara CA,
    Christie Marrian - San Jose CA,
    Bryan Choo - Mountain View CA,
    Fei Wang - San Jose CA,
    Jeffrey A. Shields - Sunnyvale CA,
  • Assignee:
    Spansion LLC - Sunnyvale CA
  • International Classification:
    H01L 29/94
    H01L 27/108
  • US Classification:
    257310, 257295, 257296, 257306, 257532, 257E21272, 257E21648, 438253, 438393, 438396, 438644, 438654
  • Abstract:
    The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the opening.
  • Test Structures For Development Of Metal-Insulator-Metal (Mim) Devices

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  • US Patent:
    8084770, Dec 27, 2011
  • Filed:
    Nov 17, 2008
  • Appl. No.:
    12/313089
  • Inventors:
    Steven Avanzino - Cupertino CA,
    Suzette K. Pangrle - Cupertino CA,
    Manuj Rathor - Milpitas CA,
    An Chen - Sunnyvale CA,
    Sameer Haddad - San Jose CA,
    Nicholas Tripsas - San Jose CA,
    Matthew Buynoski - Palo Alto CA,
  • Assignee:
    Spansion LLC - Sunnyvale CA
  • International Classification:
    H01L 29/10
  • US Classification:
    257 48, 257532, 257E21521, 257E21524, 257E29343
  • Abstract:
    In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor is exposed for access thereto.

Resumes

Suzette Pangrle Photo 1

Suzette Pangrle Northern California

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Work:
Vertical Circuits, Inc
Scotts Valley, CA
May 2009 to Jul 2012
Principal Scientist, Advanced Process Technology Lead, Technology Reliability & FA
Spansion
Sunnyvale, CA
Mar 2006 to Feb 2009
Sr. Member of Technical Staff, Device Technology (Integration) Engineer
Spansion
Sunnyvale, CA
Jan 2003 to Feb 2006
Sr. MTS, Advance Memory Research Group, Device Technology (Integration) Engineer
AMD
Sunnyvale, CA
May 1995 to Jan 2003
Member of Technical Staff, Sr. Development Engineer Advanced Process Development Engineer
Education:
University of CA, UCSC
2012 to 2013
Project & Program Management Certification (in progress)
Pennsylvania State University, State College
Ph.D. in Ceramic Science
University of Illinois
M.S. in Metallurgy
University of Illinois
Urbana-Champaign, IL
B.S. in Chemical Engineering
Skills:
Project Management Device Technology Integration Technology Transfer Operations Strategy Material Science Reliability and Failure Analysis Innovation Problem-Solving Team Strategy Technical Writing Management Reports Patents Oral/Written Communications

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Suzette Pangrle

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