Atoptech since Mar 2010
Applications Engineer
Symmid Semiconductor Technology Oct 2006 - May 2009
Design Engineer
Information Technology Program, USC Oct 2004 - Feb 2006
Systems/Network Specialist
I2 Technologies Jun 2003 - Jan 2004
Software Engineer
Education:
University of Southern California 2004 - 2005
MS, Electrical Engineering (VLSI Design)
National Institute of Technology Calicut 1998 - 2002
B.Tech, Electrical & Electronics Engineering
Skills:
Static Timing Analysis Physical Design Asic Eda Verilog Place and Route Timing Closure Primetime Lvs Drc Soc Logic Synthesis Floorplanning Clock Tree Synthesis Formal Verification Rtl Coding Cadence Timing Application Specific Integrated Circuits