Steven Mark Waldstein

US Patent:

7112990, Sep 26, 2006

Filed:

Jan 16, 2004

Appl. No.:

10/759756

Inventors:

Steven M. Waldstein - Scarborough ME, US
Maurice Richard - Gorham ME, US
Alexander Alexeyev - Yarmouth ME, US
David Reynolds - Scarborough ME, US

Assignee:

Tundra Semiconductor Corp.

International Classification:

H03K 17/16
G11C 5/14

US Classification:

326 32, 326 33, 326 34, 327530, 327534, 327157

Abstract:

Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.

US Patent:

7355467, Apr 8, 2008

Filed:

Aug 14, 2006

Appl. No.:

11/504400

Inventors:

Steven M. Waldstein - Scarborough ME, US
Maurice Richard - Gorham ME, US
Alexander Alexeyev - Yarmouth ME, US
David Reynolds - Scarborough ME, US

Assignee:

Tundra Semiconductor Corporation - Ottawa

International Classification:

G11C 5/14

US Classification:

327530, 327534, 327157

Abstract:

Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.

US Patent:

8255576, Aug 28, 2012

Filed:

Jun 15, 2010

Appl. No.:

12/815552

Inventors:

James A. Siulinski - Westbrook ME, US
Steven M. Waldstein - Scarborough ME, US

Assignee:

Patriot Funding, LLC - Great Falls VA

International Classification:

G06F 3/00
G06F 13/12
H04N 7/16

US Classification:

710 2, 710 8, 710 15, 710 36, 710 62, 725143

Abstract:

This document discusses, among other things, a system and method for switching serialized video information (e. g. , non-packet-based video information) and Universal Serial Bus (USB) information (e. g. , packet-based information) to a common output (e. g. , to a physical USB interface).

US Patent:

8316164, Nov 20, 2012

Filed:

Jun 15, 2010

Appl. No.:

12/815563

Inventors:

James A. Siulinski - Westbrook ME, US
Steven M. Waldstein - Scarborough ME, US

Assignee:

Patriot Funding, LLC - Great Falls VA

International Classification:

G06F 13/12
H04N 7/18
H04N 7/173

US Classification:

710 71, 725 74, 725105

Abstract:

This document discusses, among other things, a system and method for deserializing non-packet-based video information received using a physical Universal Serial Bus (USB) interface and providing a high definition output signal to a video port (e. g. , an HD video port, such as HDMI, DisplayPort, etc. ) using the deserialized video information.

US Patent:

8536924, Sep 17, 2013

Filed:

Sep 2, 2010

Appl. No.:

12/874832

Inventors:

Andrew M. Jordan - Scarborough ME, US
Hrvoje Jasa - Scarborough ME, US
Steven M. Waldstein - Scarborough ME, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H03L 5/00

US Classification:

327310, 327318, 327319, 327320

Abstract:

Apparatus and methods for an integrated circuit, high-impedance network are provided. In an example, the network can include an anti-parallel diode pair coupled between first and second nodes. The anti-parallel diode pair can include a first diode including a P+/Njunction and a second diode including N+/Pjunction. In an example, the first diode and the second diode can include a common substrate.

US Patent:

20110129098, Jun 2, 2011

Filed:

Oct 28, 2010

Appl. No.:

12/913897

Inventors:

Cary L. Delano - Los Altos CA, US
Steven M. Waldstein - Scarborough ME, US

International Classification:

G10K 11/16

US Classification:

381 7111, 381 711, 381 718

Abstract:

This document discusses, among other things, systems and methods for active noise cancellation. One example system includes a digital ANC circuit configured to receive first audio information from a first microphone and to produce an a digital anti-noise signal configured to attenuate noise sensed by the first microphone; an analog ANC circuit configured to receive second audio information from a second microphone and to produce an analog anti-noise signal configured to attenuate noise sensed by the second microphone; and wherein the system is configured to receive an intended audio signal and to provide an output signal for a speaker using the intended audio signal, the analog anti-noise signal, and the digital anti-noise signal.

US Patent:

20130086297, Apr 4, 2013

Filed:

Nov 19, 2012

Appl. No.:

13/680916

Inventors:

Patriot Funding, LLC - Great Falls VA, US
Steven M. Waldstein - Scarborough ME, US

Assignee:

Patriot Funding, LLC - Great Falls VA

International Classification:

G06F 13/40

US Classification:

710316

Abstract:

This document discusses, among other things, a system and method for serializing a video signal and providing non-packet-based serialized video information to a physical Universal Serial Bus (USB) interface and, in certain examples, receiving the non-packet-based serialized video information from the physical USB interface, deserializing the received non-packet-based serialized video information, and providing a high definition output signal to a video port (e.g., an HD video port, such as HDMI, DisplayPort, etc.) using the deserialized video information.

US Patent:

54045606, Apr 4, 1995

Filed:

Jun 25, 1993

Appl. No.:

8/083852

Inventors:

Raymond Y. Lee - Salem NH
Jeffrey M. Bessolo - Groton MA
Vyomesh Shah - Tewksbury MA
Scott D. Vincelette - Bethlehem PA
Steven M. Waldstein - Westford MA
Jeffrey D. Nathan - Andover MA
Steven E. Lang - Lincoln Center MA

Assignee:

Wang Laboratories, Inc. - Lowell MA

International Classification:

G06F 1500

US Classification:

395800

Abstract:

A central processing unit (CPU) 10 comprises an external control memory for storing microinstructions which correspond to macroinstructions read from a system memory. The microinstructions are 56 bits in length and are read in 28-bit segments. CPU 10 also comprises an internal memory management unit (MMU) 18 which comprises a plurality of address translation entry (ATE) registers four of which are permanent and sixteen of which are temporary in that the storage of a new translation entry occurs in a least recently used temporary translation entry register. CPU 10 also comprises a plurality of status register bits, some of which are settable only by predefined microinstructions. All of the status register bits are branchable. CPU 10 further comprises a condition code register the state of which may be determined by input signal pins. CPU 10 also comprises address generation logic which may generate a 24, 31 or 32 bit address upon a 32-bit address bus.