Steven C Eplett

US Patent:

6407608, Jun 18, 2002

Filed:

Mar 18, 1999

Appl. No.:

09/271461

Inventors:

Jason M. Brown - Stafford TX
Steven C. Eplett - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 300

US Classification:

327291, 327294, 327379, 327389

Abstract:

A clock buffer circuit ( ) for generating buffered clock signals (CLKI and CLKI_) in response to an external clock signal (CLKX) is disclosed. A first buffer section ( ) drives to a first output node ( ) between high and low logic levels in reponse the CLKX signal. To reverse the adverse effects of noise on the falling edges of CLKX signal, a boost section ( ) and clock generator ( ) are provided. In response to low-to-high transitions at the first output node ( ) the pulse generator ( ) generates a pulse at a pulse output ( ). In response to the pulse, the boost section ( ) provides additional driving capability for further pulling the first output node ( ) to the high logic level. The first output node provides the CLKI_ signal. A second buffer circuit ( ) provides the CLKI signal in response to the CLKI_ signal. An enabling section ( ) is provided for enabling, or alternatively, disabling the preferred embodiment ( ).

US Patent:

7840927, Nov 23, 2010

Filed:

Dec 8, 2007

Appl. No.:

11/953048

Inventors:

Harold Wallace Dozier - Dallas TX, US
Steven Craig Eplett - Fremont CA, US
Pat Y. Hom - Milpitas CA, US

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716 9, 716 4, 716 5, 716 6, 716 7

Abstract:

An integrated circuit implementation methodology uses mutable cells, e. g. cells that are capable of being personalized for use as one of a plurality of resource types. For example, a mutable cell is designed to have a component layout and a set of lower-layer internal connections compatible with both a design of a flip-flop, and a design of a pair of multiplexers. Independent customizations of the mutable cell, using higher layers of interconnect, efficiently use the cell as a flip-flop or as a pair of multiplexers. Use of mutable cells in an integrated circuit advantageously enables a set of predefined lower-layer photomask, such as for a predefined base array, to be efficiently shared among different applications. In some embodiments, a Simultaneous Dynamical Integration (SDI) Electronic Design Automation (EDA) flow advantageously uses mutable cells, such as to balance demand for resources against supply thereof.

US Patent:

8122413, Feb 21, 2012

Filed:

Jun 9, 2007

Appl. No.:

12/303938

Inventors:

Pat Hom - Milpitas CA, US
Steven Eplett - Milpitas CA, US
Rabi Sengupta - San Jose CA, US
Eric West - San Jose CA, US
Lyle Smith - Santa Clara CA, US

Assignee:

Otrsotech, Limited Liability Company - Wilmington DE

International Classification:

G06F 17/50

US Classification:

716116, 716104

Abstract:

Logic blocks for IC designs (including gate-array, standard cell, or logic array designs) provide Design-for-Test-enabled flip-flops (DFT-enabled FFs) that inherently insure compliance with DFT rules associated with scan shifting. Test scan-chains are configured by daisy-chaining instances of the logic block in a transparent (invisible) manner to user-designed application circuits, which can be designed without any user-inserted test structures or other regard for DFT considerations. User asynchronous set and reset inputs and all Stuck-At faults on all user pins on these DFT-enabled FFs are observable via capture and scan-out. A first type of these DFT-enabled FFs features addressable control to partition test the application circuit. A second type of these DFT-enabled FFs features integral capture buffering that eliminates the need for partition test, simplifying control logic and reducing the number of test vectors needed.

US Patent:

60231815, Feb 8, 2000

Filed:

Mar 13, 1998

Appl. No.:

9/039012

Inventors:

Daniel B. Penny - Houston TX
Steven C. Eplett - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 104

US Classification:

327291

Abstract:

A two stage input buffer substantially reduces propagation delay by triggering only off of the rising edge of the external clock signal, eliminating a pulse generator, and setting the pulse width via feedback through a fixed delay. An unbalanced driver reduces capacitance on the N-channel transistor. In a memory application, such as in a synchronous dynamic random access memory, access time is improved, margin is advantageously added to the hold time requirement, and driver fan out capabilities are improved.

US Patent:

61341681, Oct 17, 2000

Filed:

Jun 8, 1999

Appl. No.:

9/327734

Inventors:

Matthew R. Harrington - Sugar Land TX
Steven C. Eplett - Houston TX
Kallol Mazumder - Calcutta, IN
Scott E. Smith - Sugar Land TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 700

US Classification:

365222

Abstract:

A counter (450) for generating a series of binary addresses, each of the addresses including a set of one or more most-significant bits. The counter includes circuitry to generate the addresses, including the set of most-significant bits (402), in a first mode and circuitry to generate the addresses (400), excluding the set of most significant bits, in a second mode. The counter is operable to transition between the first and second modes. The counter also includes circuitry to generate the addresses in the first mode in a non-binary count order in which the set of most-significant address bits is a set of least-significant bits in the count order.

US Patent:

59994738, Dec 7, 1999

Filed:

Apr 21, 1998

Appl. No.:

9/063506

Inventors:

Matthew R. Harrington - Sugar Land TX
Steven C. Eplett - Houston TX
Kallol Mazumder - West Bengal, IN
Scott E. Smith - Sugar Land TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 700

US Classification:

365222

Abstract:

A counter (450) for generating a series of binary addresses, each of the addresses including a set of one or more most-significant bits. The counter includes circuitry to generate the addresses, including the set of most-significant bits (402), in a first mode and circuitry to generate the addresses (400), excluding the set of most significant bits, in a second mode. The counter is operable to transition between the first and second modes. The counter also includes circuitry to generate the addresses in the first mode in a non-binary count order in which the set of most-significant address bits is a set of least-significant bits in the count order.

US Patent:

60882743, Jul 11, 2000

Filed:

Feb 18, 1999

Appl. No.:

9/252169

Inventors:

Timothy D. Dorney - Houston TX
Steven C. Eplett - Houston TX
Rishad S. Omer - Sugar Land TX
John E. Riley - Katy TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 700

US Classification:

365201

Abstract:

A method and apparatus for testing a semiconductor serial access memory (30) device through a main memory (20) includes a semiconductor memory comprising a main memory (20) and a serial access memory (30). A test data (48) is generated and an expected test data (50) that is equivalent to the test data (48) is also generated. The test data (48) is stored in the main memory and sent to the serial access memory (30). The test data (48) in the serial access memory is then sent back to the main memory (20) and stored in the main memory (20). The test data (48) is then read from the main memory (20). Then, the test data (48) read from the main memory is compared with the expected test data (50), producing an output having a first state if the test data (48) read from the main memory (20) is similar to the expected test data (50) or a second state if the test data (48) read from the main memory (20) is different than the expected test data (50).