Steve Xiaofeng Chi

US Patent:

7859134, Dec 28, 2010

Filed:

Dec 21, 2007

Appl. No.:

12/005056

Inventors:

Steve X. Chi - Cupertino CA, US
Yongliang Wang - Saratoga CA, US
Ekram Hossain Bhuiyan - San Jose CA, US
Daniel P. Nguyen - Campbell CA, US
Vincent Anthony Condito - San Jose CA, US
Po-Shen Lai - San Jose CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

H02J 1/00
H02J 3/00

US Classification:

307 80

Abstract:

A method for operating an electronic product having an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product selects a low-power sub-module or high-power sub-module of the capless regulator module for use in a power-up phase of the ASIC. Control logic of the ASIC determines if an external capacitance is present. If so, then the high-power capless sub-module is used during a power-up phase of the ASIC; if not only the low-power capless sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.

US Patent:

7875996, Jan 25, 2011

Filed:

Dec 21, 2007

Appl. No.:

12/005144

Inventors:

Daniel P. Nguyen - Campbell CA, US
Steve X. Chi - Cupertino CA, US
Po-Shen Lai - San Jose CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

H02J 1/00
H02J 3/00

US Classification:

307 80

Abstract:

An electronic product includes an application specific semiconductor chip (ASIC) device which includes in its circuitry both a linear regulator module configured to be coupled to an optional external capacitance and a capless regulator module configured to be coupled to internal capacitance of the electronic product. Control logic of the ASIC device is responsive to a regulator selection signal for selecting one of the linear regulator module and the capless regulator module for use in powering the ASIC device. The control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation.

US Patent:

8624652, Jan 7, 2014

Filed:

Jul 18, 2012

Appl. No.:

13/551835

Inventors:

Ekram H. Bhuiyan - San Jose CA, US
Steve X. Chi - Cupertino CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

H03H 11/26

US Classification:

327261, 327263, 327268

Abstract:

Delay circuits are described for which the delay remains substantially constant within a desired range of variation of supply voltage and/or temperature.

US Patent:

20090160256, Jun 25, 2009

Filed:

Dec 21, 2007

Appl. No.:

12/005124

Inventors:

Daniel P. Nguyen - Campbell CA, US
Steve X. Chi - Cupertino CA, US
Po-Shen Lai - San Jose CA, US

International Classification:

H02J 1/00

US Classification:

307 80

Abstract:

A method for operating an electronic product having an application specific semiconductor chip (ASIC) device which includes in its circuitry both a linear regulator module configured to be coupled to an optional external capacitance and a capless regulator module configured to be coupled to internal capacitance of the electronic product utilizes control logic of the ASIC device responsive to a regulator selection signal for selecting one of the linear regulator module and the capless regulator module for use in powering the ASIC device. The control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation.

US Patent:

20090160423, Jun 25, 2009

Filed:

Dec 21, 2007

Appl. No.:

12/005126

Inventors:

Steve X. Chi - Cupertino CA, US
Yongliang Wang - Saratoga CA, US
Ekram Hossain Bhuiyan - San Jose CA, US
Daniel P. Nguyen - Campbell CA, US
Vincent Anthony Condito - San Jose CA, US
Po-Shen Lai - San Jose CA, US

International Classification:

G05B 13/02

US Classification:

323352

Abstract:

An electronic product includes an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product. The capless regulator module includes both a low-power sub-module and a high-power sub-module. Control logic of the ASIC is configured to determine if an external capacitance is present. If so, the control logic causes the high-power capless regulator sub-module to be used during a power-up phase of the ASIC; if not, only the low-power capless regulator sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.

US Patent:

20090167093, Jul 2, 2009

Filed:

Dec 28, 2007

Appl. No.:

11/965943

Inventors:

Daniel P. Nguyen - Campbell CA, US
Steve X. Chi - Cupertino CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

H02J 1/00
H02J 3/00
H03L 7/00
G01R 19/00

US Classification:

307 80, 307 43, 327143, 324 7611

Abstract:

Methods and systems for automatically and/or locally adjusting power-valid detection. In one class of embodiments, local power-on-reset circuits are included in individual power islands; in another class of embodiments, the power-on-reset circuit is automatically reprogrammed, depending on the detected interface voltage level, to use the same circuitry for power-valid detection in either case.

US Patent:

20110133710, Jun 9, 2011

Filed:

Dec 8, 2009

Appl. No.:

12/632998

Inventors:

Deepak Pancholi - Bangalore, IN
Ekram Bhuiyan - San Jose CA, US
Steve Chi - Cupertino CA, US
Naidu Prasad - New Tippasandra, IN
Bhavin Odedara - Kodihalli, IN

International Classification:

G05F 1/10

US Classification:

323280

Abstract:

Techniques are presented for reducing the DC voltage shift in a voltage regulator, particularly for high and ultra-high speed load switching operation. The regulator includes a power transistor, connected between an input supply voltage and an output node, and an error amplifier, having its output connected to control the gate of the output transistor, a first input connected to receive a reference voltage, and a second input connected to a feedback node. The regulator also includes a first resistance, connected between the feedback node and ground, and also a second resistance, a third resistance, and a first capacitance, where the feedback node is connected to the output node through a combination of the first capacitance in parallel with the second resistance and in series with the third resistance. Consequently, the feedback path from the output node of the regulator uses a partial feedback mechanism, where the capacitance is included to generate a zero in the feedback divider path, but a resistance is placed in series with the capacitance so that at high frequencies the feedback level is still separated from the output level.

US Patent:

20110234268, Sep 29, 2011

Filed:

Mar 26, 2010

Appl. No.:

12/748345

Inventors:

Steve Chi - Cupertino CA, US
Ekram Bhuiyan - San Jose CA, US

Assignee:

SanDisk Corp. - Milpitas CA

International Classification:

H03L 7/00

US Classification:

327143

Abstract:

A host power-on reset control circuit includes a comparator connected to receive both a divided version of a supply voltage and a reference voltage. The comparator generates and outputs a high digital state signal when the divided version of the supply voltage is at least as large as the reference voltage. The control circuit includes an output node connected to transmit a power-on reset control signal. The control circuit includes pulldown circuitry connected between the comparator output and the output node. The pulldown circuitry maintains the output node at a reset voltage level as the supply voltage rises to a host operational level, based on a signal present at the comparator output. The control circuit includes pullup circuitry connected between the supply voltage and the output node. The pullup circuitry maintains the output node at a non-reset voltage level after the supply voltage has risen to the host operational level.