Stephen Ray Deiss

US Patent:

20110043225, Feb 24, 2011

Filed:

Nov 26, 2008

Appl. No.:

12/744921

Inventors:

Thomas J. Sullivan - San Diego CA, US
Gert Cauwenberghs - San Diego CA, US
Stephen R. Deiss - San Diego CA, US

Assignee:

THE REGENTS OF THE UNIVERSITY OF CALIFORNIA - Oakland CA

International Classification:

G01R 27/26

US Classification:

324658

Abstract:

A capacitive sensor system including a sensing plate, an amplifier, and a switching circuit is described. The sensing plate is capacitively coupled to a body surface. A change in the electric potential on the body surface generates an electric field that induces change in the electric potential of the sensing plate. The sensing plate includes a sensing node positioned in the electric field for generating an input signal from the electric field. The sensing plate is not in contact with the body surface. The amplifier receives the input signal at the input port, amplifies the input signal and generates an output signal at the output port. The switching circuit is connected to the input port and a reference voltage. The switching circuit non-continuously closes a shunting path from the sensing node to the reference voltage to reset the voltage at the sensing node.

US Patent:

49741462, Nov 27, 1990

Filed:

May 6, 1988

Appl. No.:

7/191207

Inventors:

George A. Works - San Diego CA
William L. Hicks - San Diego CA
Richard L. Kasbo - San Diego CA
Ernest E. Muenchau - San Diego CA
Stephen R. Deiss - Encinitas CA

Assignee:

Science Applications International Corporation - San Diego CA

International Classification:

G06F 15347

US Classification:

364200

Abstract:

A four stage pipelined processor (40) provides efficient processing of the most common operation performed in simulating neuron networks. A first stage of the processor includes a program memory (42) and a program address generator (41). A second stage comprises first and second data memories (44, 46) and respective address generators (60, 66) coupled thereto. A third stage comprises the input (X, Y) of a function unit (82), and a fourth stage comprises the output (Z) of the function unit (82). A unique bus architecture allows the various stages to simultaneously communicate with each other through the use of independent buses, and further provides for the quick simultaneous transfer of data from both the first and second data memories to the function unit. When not needed for performing in the pipelined mode, the various buses may be coupled together and to an I/O interface (52) by means of bus coupling means (e. g. , 47). This architecture significantly reduces the circuitry needed to implement the necessary buses while allowing the processor to run without speed limitations in the pipelined mode.