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Srinivas Vr Pietambaram

age ~49

from Chandler, AZ

Also known as:
  • Srinivas V Pietambaram
  • Srinivas V Pietambalam
  • Pietambaram V Srini
  • Sriniva Pietambalam
  • Pietambaram Srinivas

Srinivas Pietambaram Phones & Addresses

  • Chandler, AZ
  • 4451 E Maplewood St, Gilbert, AZ 85297 • 480-963-0084
  • Gainesville, FL
  • Maricopa, AZ
  • Austin, TX

Work

  • Company:
    Everspin technologies, inc.
    Jun 2008
  • Position:
    Materials r&d

Education

  • Degree:
    Ph.D.
  • School / High School:
    University of Florida
    1997 to 2001
  • Specialities:
    Materials Science and Engineering

Skills

Thin Films • Semiconductors • Design of Experiments • Characterization • Materials Science • Jmp • Pvd • R&D • Sensors • Electronics • Process Engineering • Failure Analysis • Spc • Semiconductor Industry • Nanotechnology • Pecvd • Cvd • Sputtering • Afm • Six Sigma • Silicon • Data Analysis • Analysis • Process Improvement and Sustaining • Data Mining • Powder X Ray Diffraction • Semiconductor Process • Tem • Metrology • Ic • Mems • Process Integration • Process Simulation • Vacuum • Materials • Fib • Cmos • Surface Chemistry • Yield • Scanning Electron Microscopy • Experimentation • Technical Writing • Technology Development • Process Development • Doe • Yield Analysis • Product Engineering • Magnetics • Research and Development

Industries

Semiconductors

Us Patents

  • Amorphous Alloys For Magnetic Devices

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  • US Patent:
    6831312, Dec 14, 2004
  • Filed:
    Aug 30, 2002
  • Appl. No.:
    10/232164
  • Inventors:
    Jon M. Slaughter - Tempe AZ
    Renu W. Dave - Chandler AZ
    Srinivas V. Pietambaram - Chandler AZ
  • Assignee:
    Freescale Semiconductor, Inc. - Austin TX
  • International Classification:
    H01L 31119
  • US Classification:
    257295, 257489
  • Abstract:
    An amorphous layer of a cobalt iron-based (CoFe-based) magnetic alloy suitable for use in magnetoelectronic devices is disclosed. In the most preferred embodiments of the present invention, at least one amorphous layer is provided in an MTJ stack to increase the smoothness of the various layers in the MTJ stack while also enhancing the magnetic performance of the resulting device. Additionally, the alloys of the present invention are also useful in cladding applications to provide electrical flux containment for signal lines in magnetoelectronic devices and as a material for fabricating write heads.
  • Synthetic Antiferromagnet Structures For Use In Mtjs In Mram Technology

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  • US Patent:
    6946697, Sep 20, 2005
  • Filed:
    Dec 18, 2003
  • Appl. No.:
    10/740338
  • Inventors:
    Srinivas V. Pietambaram - Chandler AZ, US
    Renu W. Dave - Chandler AZ, US
    Jon M. Slaughter - Tempe AZ, US
    Jijun Sun - Chandler AZ, US
  • Assignee:
    Freescale Semiconductor, Inc. - Austin TX
  • International Classification:
    H01L029/76
  • US Classification:
    257295, 257421, 365158, 365171, 365173
  • Abstract:
    A magnetic tunnel junction (MTJ), which is useful in magnetoresistive random access memories (MRAMs), has a free layer which is a synthetic antiferromagnet (SAF) structure. This SAF is composed of two ferromagnetic layers that are separated by a coupling layer. The coupling layer has a base material that is non-magnetic and also other materials that improve thermal endurance, control of the coupling strength of the SAF, and magnetoresistance ratio (MR). The preferred base material is ruthenium and the preferred other material is tantalum. Furthering these benefits, cobalt-iron is added at the interface between the tantalum and one of the ferromagnetic layers. Also the coupling layer can have even more layers and the materials used can vary. Also the coupling layer itself can be an alloy.
  • Method Of Making Amorphous Alloys For Semiconductor Device

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  • US Patent:
    7067331, Jun 27, 2006
  • Filed:
    Nov 3, 2004
  • Appl. No.:
    10/980930
  • Inventors:
    Jon M. Slaughter - Tempe AZ, US
    Renu W. Dave - Chandler AZ, US
    Srinivas V. Pietambaram - Chandler AZ, US
  • Assignee:
    Freescale Semiconductor, Inc. - Austin TX
  • International Classification:
    H01L 21/00
  • US Classification:
    438 3, 438 73
  • Abstract:
    An amorphous layer of a cobalt iron-based (CoFe-based) magnetic alloy suitable for use in magnetoelectronic devices is disclosed. In the most preferred embodiments of the present invention, at least one amorphous layer is provided in an MTJ stack to increase the smoothness of the various layers in the MTJ stack while also enhancing the magnetic performance of the resulting device. Additionally, the alloys of the present invention are also useful in cladding applications to provide electrical flux containment for signal lines in magnetoelectronic devices and as a material for fabricating write heads.
  • Synthetic Antiferromagnet Structures For Use In Mtjs In Mram Technology

    view source
  • US Patent:
    7226796, Jun 5, 2007
  • Filed:
    Jul 15, 2005
  • Appl. No.:
    11/182149
  • Inventors:
    Srinivas V. Pietambaram - Chandler AZ, US
    Renu W. Dave - Chandler AZ, US
    Jon M. Slaughter - Tempe AZ, US
    Jijun Sun - Chandler AZ, US
  • Assignee:
    Freescale Semiconductor, Inc. - Austin TX
  • International Classification:
    H01L 21/00
    H01L 29/76
  • US Classification:
    438 3, 257295, 257E21665, 365158, 365171, 365173, 4288112
  • Abstract:
    A magnetic tunnel junction (MTJ), which is useful in magnetoresistive random access memories (MRAMs), has a free layer which is a synthetic antiferromagnet (SAF) structure. This SAF is composed of two ferromagnetic layers that are separated by a coupling layer. The coupling layer has a base material that is non-magnetic and also other materials that improve thermal endurance, control of the coupling strength of the SAF, and magnetoresistance ratio (MR). The preferred base material is ruthenium and the preferred other material is tantalum. Furthering these benefits, cobalt-iron is added at the interface between the tantalum and one of the ferromagnetic layers. Also the coupling layer can have even more layers and the materials used can vary. Also the coupling layer itself can be an alloy.
  • Low Power Magnetoelectronic Device Structures Utilizing Enhanced Permeability Materials

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  • US Patent:
    7285835, Oct 23, 2007
  • Filed:
    Feb 24, 2005
  • Appl. No.:
    11/066884
  • Inventors:
    Nicholas D. Rizzo - Gilbert AZ, US
    Renu Dave - Chandler AZ, US
    Jon M. Slaughter - Tempe AZ, US
    Srinivas V. Pietambaram - Chandler AZ, US
  • Assignee:
    Freescale Semiconductor, Inc. - Austin TX
  • International Classification:
    H01L 43/00
  • US Classification:
    257421, 257295, 257E27006, 438 3, 365171
  • Abstract:
    Low power magnetoelectronic device structures and methods for making the same are provided. One magnetoelectronic device structure () comprises a programming line (), a magnetoelectronic device () magnetically coupled to the programming line, and an enhanced permeability dielectric material () disposed adjacent the magnetoelectronic device. The enhanced permeability dielectric material has a permeability no less than approximately 1. 5. A method for making a magnetoelectronic device structure is also provided. The method comprises fabricating a magnetoelectronic device () and depositing a conducting line (). A layer of enhanced permeability dielectric material () having a permeability no less than approximately 1. 5 is formed, wherein after the step of fabricating a magnetoelectronic device and the step of depositing a conducting line, the layer of enhanced permeability dielectric material is situated adjacent the magnetoelectronic device.
  • Magnetic Tunnel Junction Memory And Method With Etch-Stop Layer

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  • US Patent:
    7445943, Nov 4, 2008
  • Filed:
    Oct 19, 2006
  • Appl. No.:
    11/584411
  • Inventors:
    Kenneth H. Smith - Chandler AZ, US
    Brian R. Butcher - Queen Creek AZ, US
    Gregory W. Grynkewich - Gilbert AZ, US
    Srinivas V. Pietambaram - Chandler AZ, US
    Nicholas D. Rizzo - Gilbert AZ, US
  • Assignee:
    Everspin Technologies, Inc. - Chandler AZ
  • International Classification:
    H01L 21/00
  • US Classification:
    438 3, 438733, 257E2117, 257E21208, 257E21209, 257E21218, 257E21231, 257E21646
  • Abstract:
    Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (), first () and second () electrodes coupled, respectively, to first () and second () magnetic layers of the MTJ (), first () and second () write conductors magnetically coupled to the MTJ () and spaced apart from the first () and second () electrodes, and at least one etch-stop layer () located between the first write conductor () and the first electrode (), having an etch rate in a reagent for etching the MTJ () and/or the first electrode () that is at most % of the etch rate of the MTJ () and/or first conductor () to the same reagent, so as to allow portions of the MTJ () and first electrode () to be removed without affecting the underlying first write conductor (). In a further embodiment, a second etch-stop layer () is located between the second electrode () and the second write conductor (). Improved yield and performance are obtained.
  • Low Power Magnetoelectronic Device Structures Utilizing Enhanced Permeability Materials

    view source
  • US Patent:
    7635902, Dec 22, 2009
  • Filed:
    Oct 4, 2007
  • Appl. No.:
    11/867189
  • Inventors:
    Nicholas D. Rizzo - Gilbert AZ, US
    Renu Dave - Chandler AZ, US
    Jon M. Slaughter - Tempe AZ, US
    Srinivas V. Pietambaram - Chandler AZ, US
  • Assignee:
    Everspin Technologies, Inc. - Chandler AZ
  • International Classification:
    H01L 29/82
  • US Classification:
    257421, 257295, 257E27006, 438 3, 977838, 977933, 365171
  • Abstract:
    Low power magnetoelectronic device structures and methods for making the same are provided. One magnetoelectronic device structure () comprises a programming line (), a magnetoelectronic device () magnetically coupled to the programming line, and an enhanced permeability dielectric material () disposed adjacent the magnetoelectronic device. The enhanced permeability dielectric material has a permeability no less than approximately 1. 5. A method for making a magnetoelectronic device structure is also provided. The method comprises fabricating a magnetoelectronic device () and depositing a conducting line (). A layer of enhanced permeability dielectric material () having a permeability no less than approximately 1. 5 is formed, wherein after the step of fabricating a magnetoelectronic device and the step of depositing a conducting line, the layer of enhanced permeability dielectric material is situated adjacent the magnetoelectronic device.
  • Enhanced Permeability Device Structures And Method

    view source
  • US Patent:
    7683445, Mar 23, 2010
  • Filed:
    Apr 25, 2007
  • Appl. No.:
    11/740066
  • Inventors:
    Srinivas V. Pietambaram - Chandler AZ, US
    Nicholas D. Rizzo - Gilbert AZ, US
    Jon M. Slaughter - Tempe AZ, US
  • Assignee:
    Everspin Technologies, Inc. - Chandler AZ
  • International Classification:
    H01L 29/82
  • US Classification:
    257421, 257295, 257E27006, 438 3, 977838, 977933, 365171
  • Abstract:
    Low power magnetoelectronic device structures and methods therefore are provided. The magnetoelectronic device structure () comprises a programming line (), a magnetoelectronic device () magnetically coupled to the programming line (), and an enhanced permeability dielectric (EPD) material () disposed adjacent the magnetoelectronic device. The EPD material () comprises multiple composite layers () of magnetic nano-particles () embedded in a dielectric matrix (). The composition of the composite layers is chosen to provide a predetermined permeability profile. A method for making a magnetoelectronic device structure is also provided. The method comprises fabricating the magnetoelectronic device () and depositing the programming line (). The EPD material () comprising the multiple composite layers () is formed around the magnetoelectronic device () and/or between the device () and the programming line (). The presence of the EPD structure () in proximity to the programming line () and/or the magnetoelectronic device () reduces the required programming current.

Resumes

Srinivas Pietambaram Photo 1

Technologist, Packaging Technology Development

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Location:
Phoenix, AZ
Industry:
Semiconductors
Work:
EverSpin Technologies, Inc. since Jun 2008
Materials R&D

Freescale Semiconductor Dec 2004 - Jun 2008
Materials R&D

Motorola Aug 2001 - Dec 2004
Materials R&D

Motorola May 1998 - Aug 1998
Summer Intern '98, '99, '00
Education:
University of Florida 1997 - 2001
Ph.D., Materials Science and EngineeringDissertation: Fabrication and Characterization of Magneto-transport in Colossal Magnetoresistive Oxide Films and Hybrid Structures > Optimized various deposition parameters in Pulsed Laser Deposition to produce good quality manganite thin films with high reproducibility > Investigated novel hybrid structures – Magnetic tunnel junctions utilizing high quality manganite films as one or both electrodes. In case where manganite films are used as one of the electrodes, sputter deposited magnetic metallic films are used as the other electrode > Studied magneto-transport and magnetic properties in these Colossal Magnetoresistive Oxide Films (manganites) and Hybrid Structures > Characterized these structures by XRD, AFM, TEM, and RBS > Published research in prestigious journals and presented at international conferences Awards: Certificate of award for academic achievement by an international student
National Institute of Technology Rourkela 1992 - 1996
Bachelor of Engineering, Metallurgical EngineeringRecipient of Metallurgical Engineering Association Gold medal awarded for the best graduate from the Department of Metallurgical Engineering; Merit Scholarship through out undergraduate studies
Hindu College, Guntur 1990 - 1992
Intermediate, Mathematics, Physics, Chemistry
Skills:
Thin Films
Semiconductors
Design of Experiments
Characterization
Materials Science
Jmp
Pvd
R&D
Sensors
Electronics
Process Engineering
Failure Analysis
Spc
Semiconductor Industry
Nanotechnology
Pecvd
Cvd
Sputtering
Afm
Six Sigma
Silicon
Data Analysis
Analysis
Process Improvement and Sustaining
Data Mining
Powder X Ray Diffraction
Semiconductor Process
Tem
Metrology
Ic
Mems
Process Integration
Process Simulation
Vacuum
Materials
Fib
Cmos
Surface Chemistry
Yield
Scanning Electron Microscopy
Experimentation
Technical Writing
Technology Development
Process Development
Doe
Yield Analysis
Product Engineering
Magnetics
Research and Development

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