- Santa Clara CA, US Hao Luo - Milpitas CA, US Somnath Kundu - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03B 5/06 H03B 5/36 H03B 5/12
Abstract:
An apparatus injects a start clock to a crystal at the beginning to increase an overall start up speed of the crystal. The apparatus relies on an impedance change inside the crystal itself instead of searching for a synchronization on the yet small crystal oscillation. The apparatus includes an oscillator (separate from the crystal) to search for the crystal's resonance frequency by detecting the crystal's impedance change. Once the frequency of the oscillator matches the crystal's resonance, there is significant change in the crystal's impedance. Using that information, the apparatus can lock the oscillator frequency at the crystal resonance frequency and inject the clock with high efficiency.
Quadrature Local Oscillator Signal Generation Systems And Methods
- Santa Clara CA, US Alon Cohen - Petach Tikva, IL Gil Horovitz - Emek-Hefer, IL Somnath Kundu - Hillsboro OR, US Run Levinger - Tel Aviv, IL Stefano Pellerano - Beaverton OR, US Jahnavi Sharma - Hillsboro OR, US Evgeny Shumaker - Nesher, IL Izhak Hod - Haifa, IL
International Classification:
H03L 7/081 H03L 7/083
Abstract:
A quadrature based voltage controlled oscillator (VCO) local oscillator (LO) system is disclosed. The system includes a phase detector, a quadrature phase VCO, a quadrature control path, an in-phase control path, and an in-phase VCO. The phase detector is configured to compare and generate phase error between a reference clock and an in-phase VCO output. The quadrature control path configured to generate a quadrature control voltage based on a quadrature VCO output and the in-phase VCO output. The quadrature phase VCO configured to generate the quadrature VCO output based on the quadrature control voltage and the generated phase error. The in-phase control path configured to generate an in-phase control voltage based on the quadrature VCO output and the in-phase VCO output. The in-phase VCO is configured to generate the in-phase VCO output based on the in-phase control voltage and the generated phase error. An all digital dual mode phase locked/phase tracking loop LO generate system is also disclosed.
- Minneapolis MN, US Somnath Kundu - Hillsboro OR, US Hyung-il Kim - Woodbury MN, US
International Classification:
H04L 25/03 H04L 7/00
Abstract:
A time-based decision feedback equalizer (TB-DFE) circuit may include a voltage-to-time converter configured to convert a communication signal into a time-based signal. A timing of when an edge of the time-based signal occurs is indicative of a voltage level of the communication signal. The circuit may include a plurality of delay circuits arranged to process the time-based signal in series to generate a delay data signal. The delay circuits may adjust the timing of when the edge of the time-based signal occurs, and a corresponding time delay introduced by each of the delay circuits may be based on a respective weighting factor applied to one or more samples of an output digital signal previously generated by the TB-DFE circuit. A phase detector may compare a timing of an edge of the delay data signal with a reference clock signal and generate the output digital signal based on the comparison.
Intel Labs
Research Scientist
University of Minnesota Sep 2012 - Nov 2016
Graduate Research Assistant
Intel Labs Sep 2015 - Nov 2015
Graduate Technical Intern
Rambus Jun 2015 - Aug 2015
Engineering Intern
Xilinx Jun 2014 - Sep 2014
Analog Mixed Signal Intern
Education:
University of Minnesota 2012 - 2016
Doctorates, Doctor of Philosophy, Computer Engineering, Philosophy
Indian Institute of Technology, Delhi Jan 1, 2009 - 2012
Masters, Electrical Engineering
Jadavpur University Jan 1, 2004 - 2008
Bachelors, Engineering, Electronics
Midnapore Collegiate School Jan 1, 1996 - Dec 31, 2004
University of Minnesota
Indian Institute of Technology Delhi
Master of Science, Masters, Design
Indian Institute of Technology
Skills:
Vlsi Analog Analog Circuit Design Cadence Virtuoso Integrated Circuit Design Low Power Design Rf Simulations Spice Semiconductors Radio Frequency Very Large Scale Integration Spectre Microelectronics Cmos Circuit Design Eldo Mixed Signal Ic Design Agilent Ads Rf Oscillator
Aug 2012 to 2000 Graduate Research AssistantSTMicroelectronics, Analog & Mixed Signal IP Group
Jul 2010 to Jul 2012 Sr. Design Engineer (Analog)Analog & Mixed Signal IP Group
Jun 2008 to Jun 2010 Design Engineer
Education:
University of Minnesota Minneapolis-Saint Paul, MN Aug 2012 to 2000 PhD in Electrical EngineeringIndian Institute of Technology New Delhi, Delhi Jul 2009 to Jul 2012 M.S. in ResearchJadavpur University Kolkata, West Bengal Jul 2004 to Jun 2008 Bachelor of Electronics and Tele-Communication Engineering