Sidharth Bhatia

US Patent:

20080311754, Dec 18, 2008

Filed:

Jun 11, 2008

Appl. No.:

12/137372

Inventors:

BALAJI CHANDRASEKARAN - Santa Clara CA, US
Douglas E. Manning - Kuna ID, US
Nitin K. Ingle - Santa Clara CA, US
Rong Pan - San Francisco CA, US
Zheng Yuan - Fremont CA, US
Sidharth Bhatia - Sunnyvale CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/311
H01L 21/31

US Classification:

438696, 438787, 257E2124, 257E21249

Abstract:

A method of improving pattern loading in a deposition of a silicon oxide film is described. The method may include providing a deposition substrate to a deposition chamber, and adjusting a temperature of the deposition substrate to about 250 C. to about 325 C. An ozone containing gas may be introduced to the deposition chamber at a first flow rate of about 1.5 slm to about 3 slm, where the ozone concentration in the gas is about 6% to about 12%, by wt. TEOS may also be introduced to the deposition chamber at a second flow rate of about 2500 mgm to about 4500 mgm. The deposition rate of the silicon oxide film is controlled by a reaction rate of a reaction of the ozone and TEOS at a deposition surface of the substrate.

US Patent:

20120094468, Apr 19, 2012

Filed:

Jul 14, 2011

Appl. No.:

13/182671

Inventors:

Sidharth Bhatia - Menlo Park CA, US
Hiroshi Hamana - Amagasaki, JP
Paul Edward Gee - San Jose CA, US
Shankar Venkataraman - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/762
B82Y 40/00

US Classification:

438437, 977755, 257E21546

Abstract:

Aspects of the disclosure pertain to methods of depositing silicon oxide layers on substrates. In embodiments, silicon oxide layers are deposited by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor and a second silicon-containing precursor, having both a Si—C bond and a Si—N bond, into a semiconductor processing chamber to form a conformal liner layer. Upon completion of the liner layer, a gap fill layer is formed by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor into the semiconductor processing chamber. The presence of the conformal liner layer improves the ability of the gap fill layer to grow more smoothly, fill trenches and produce a reduced quantity and/or size of voids within the silicon oxide filler material.

US Patent:

20120225565, Sep 6, 2012

Filed:

Oct 3, 2011

Appl. No.:

13/251621

Inventors:

Sidharth Bhatia - Menlo Park CA, US
Paul Edward Gee - San Jose CA, US
Shankar Venkataraman - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/31

US Classification:

438763, 257E2124

Abstract:

Aspects of the disclosure pertain to methods of depositing conformal silicon oxide multi-layers on patterned substrates. The conformal silicon oxide multi-layers are each formed by depositing multiple sub-layers. Sub-layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS) and an oxygen-containing precursor into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. A plasma treatment may follow formation of sub-layers to further improve conformality and to decrease the wet etch rate of the conformal silicon oxide multi-layer film. The deposition of conformal silicon oxide multi-layers grown according to embodiments have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.

US Patent:

20070212850, Sep 13, 2007

Filed:

Mar 15, 2007

Appl. No.:

11/686863

Inventors:

Nitin Ingle - Santa Clara CA, US
Sidharth Bhatia - Sunnyvale CA, US
Won Bang - Santa Clara CA, US
Zheng Yuan - Cupertino CA, US
Ellie Yieh - San Jose CA, US
Shankar Venkatraman - Santa Clara CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/762

US Classification:

438435000, 438424000, 438782000, 257E21546

Abstract:

A chemical vapor deposition method for forming a dielectric material in a trench formed on a substrate, where the method includes the steps of generating water vapor by contacting hydrogen gas and oxygen gas with a water vapor generation catalyst, and providing the water vapor to the process chamber. The method also includes flowing a silicon-containing precursor into the process chamber housing the substrate, flowing an oxidizing gas into the chamber, and causing a reaction between the silicon-containing precursor, the oxidizing gas and the water vapor to form the dielectric material in the trench. The method may also include increasing over time a ratio of the silicon-containing precursor to the oxidizing gas flowed into the chamber to alter a rate of deposition of the dielectric material.

US Patent:

20220260978, Aug 18, 2022

Filed:

Feb 17, 2021

Appl. No.:

17/177978

Inventors:

- Santa Clara CA, US
Sidharth Bhatia - Santa Cruz CA, US
Katty Marie Lydia Gamon Guyomard - Los Altos CA, US
Shawyon Jafari - Sunnyvale CA, US
Heng-Cheng Pai - Cupertino CA, US
Pramod Nambiar - Sunnyvale CA, US
Paul Lukas Brillhart - Pleasanton CA, US
Ilker Durukan - San Jose CA, US

International Classification:

G05B 19/418
G06N 20/00
G01N 33/00
G06F 30/398

Abstract:

A method includes receiving part data associated with a corresponding part of substrate processing equipment, sensor data associated with one or more corresponding substrate processing operations performed by the substrate processing equipment to produce one or more corresponding substrates, and metrology data associated with the one or more corresponding substrates produced by the one or more corresponding substrate processing operations performed by the substrate processing equipment that includes the corresponding part. The method further includes generating sets of aggregated part-sensor-metrology data including a corresponding set of part data, a corresponding set of sensor data, and a corresponding set of metrology data. The method further includes causing analysis of the sets of aggregated part-sensor-metrology data to generate one or more outputs to perform a corrective action associated with the corresponding part of the substrate processing equipment.

US Patent:

20200381222, Dec 3, 2020

Filed:

Aug 18, 2020

Appl. No.:

16/996004

Inventors:

- Santa Clara CA, US
Prashanth KOTHNUR - San Jose CA, US
Sidharth BHATIA - Santa Cruz CA, US
Anup Kumar SINGH - Santa Clara CA, US
Vivek Bharat SHAH - Sunnyvale CA, US
Ganesh BALASUBRAMANIAN - Fremont CA, US
Changgong WANG - San Jose CA, US

International Classification:

H01J 37/32

Abstract:

Embodiments of the present disclosure generally relate to apparatuses for reducing particle contamination on substrates in a plasma processing chamber. In one or more embodiments, an edge ring is provided and includes a top surface, a bottom surface opposite the top surface and extending radially outward, an outer vertical wall extending between and connected to the top surface and the bottom surface, an inner vertical wall opposite the outer vertical wall, an inner lip extending radially inward from the inner vertical wall, and an inner step disposed between and connected to the inner wall and the bottom surface. During processing, the edge ring shifts the high plasma density zone away from the edge area of the substrate to avoid depositing particles on the substrate when the plasma is de-energized.

US Patent:

20200350146, Nov 5, 2020

Filed:

Jul 13, 2020

Appl. No.:

16/927618

Inventors:

- Santa Clara CA, US
Anup Kumar SINGH - Santa Clara CA, US
Vivek Bharat SHAH - Sunnyvale CA, US
Sidharth BHATIA - Santa Cruz CA, US
Ganesh BALASUBRAMANIAN - Fremont CA, US

International Classification:

H01J 37/32

Abstract:

A method and apparatus for operating a plasma processing chamber includes performing a plasma process at a process pressure and a pressure power to generate a plasma. A first ramping-down stage starts in which the process power and the process pressure are ramped down substantially simultaneously to an intermediate power level and an intermediate pressure level, respectively. The intermediate power level and intermediate pressure level are preselected so as to raise a plasma sheath boundary above a threshold height from a surface of a substrate. A purge gas is flowed from a showerhead assembly at a sufficiently high rate to sweep away contaminant particles trapped in the plasma such that one or more contaminant particles move outwardly of an edge of the substrate. A second ramping-down stage starts where the intermediate power level and the intermediate pressure level decline to a zero level and a base pressure, respectively.

US Patent:

20200202044, Jun 25, 2020

Filed:

Dec 16, 2019

Appl. No.:

16/716274

Inventors:

- Santa Clara CA, US
Sidharth Bhatia - Santa Clara CA, US
Garrett Ho-Yee Sin - Sunnyvale CA, US
Pramod Nambiar - Sunnyvale CA, US
Hang Yu - San Jose CA, US
Sanjay Kamath - Fremont CA, US
Deenesh Padhi - Santa Clara CA, US
Heng-Cheng Pai - Cupertino CA, US

International Classification:

G06F 30/12
G06F 16/903
G06F 16/904

Abstract:

A process development visualization tool generates a first visualization of a parameter associated with a manufacturing process, and provides a GUI control element associated with a process variable of the manufacturing process, wherein the GUI control element has a first setting associated with a first value for the process variable. The process development tool receives a user input to adjust the GUI control element from the first setting to a second setting, determines a second value for the process variable based on the second setting, and determines a second set of values for the parameter that are associated with the second value for the process variable. The process development tool then generates a second visualization of the parameter, wherein the second visualization represents the second set of values for the parameter that are associated with the second value for the process variable.