Shailesh R Chitnis

US Patent:

6970043, Nov 29, 2005

Filed:

Aug 21, 2003

Appl. No.:

10/645033

Inventors:

Pravas Pradhan - South Portland ME, US
Shailesh Chitnis - Portland ME, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H03F003/45

US Classification:

330253, 330261, 327359

Abstract:

A folded common cascode circuit with symmetric parallel signal paths from the differential inputs to a single ended output provides a low skew, low jitter, low power, high speed differential amplifier. The signal paths on either side of the differential amplifier are made equal with equal loads along each path. Pairs of complementary NMOS and PMOS transistor pairs with parallel complementary biasing current mirroring stacks on the cascode circuitry have all their gates connected together. The layout maintains symmetrical parallel signal paths and symmetrical amplification and impedance loading from differential input to output. Output inverters provide a higher drive capability.

US Patent:

7405628, Jul 29, 2008

Filed:

Sep 29, 2006

Appl. No.:

11/537082

Inventors:

Ronald B. Hulfachor - Nashua NH, US
Srisai R. Seethamraju - Nashua NH, US
Shailesh Chitnis - Nashua NH, US

Assignee:

Silicon Laboratories Inc. - Austin TX

International Classification:

H03L 7/00

US Classification:

331 11, 327147

Abstract:

A technique that is readily implemented in monolithic integrated circuits reduces or eliminates phase glitches when switching between input reference clock signals. The technique combines a pulsed phase-difference signal and a pulsed phase-difference compensation signal to substantially attenuate a DC component of the phase-difference signal and at least partially attenuate harmonic components of the phase-difference signal. The pulsed phase-difference compensation signal is based on an indicator of a phase difference between the input reference clock signals.

US Patent:

20040080369, Apr 29, 2004

Filed:

Aug 21, 2003

Appl. No.:

10/645408

Inventors:

Pravas Pradhan - South Portland ME, US
Shailesh Chitnis - Portland ME, US

International Classification:

H03F003/45

US Classification:

330/253000

Abstract:

A folded common cascode circuit with symmetric parallel signal paths from the differential inputs to a single ended output provides a low skew, low jitter, low power, high speed differential in/out amplifier. There is a differential input stage followed by a load or current summation stage with all gates tied together, and then a second differential stage. The dynamic voltage range of the second stage allows for lower Vcc operation while providing improved jitter operation. The signal paths on either side of the differential amplifier are made equal with equal loads along each path. Pairs of complementary NMOS and PMOS transistor pairs with parallel complementary biasing current mirroring stacks on the cascode circuitry have all their gates connected together. The layout maintains symmetrical parallel signal paths and symmetrical amplification and impedance loading from differential input to the differential output. Output inverters provide a higher drive capability.