Shahram C Jamshidi

US Patent:

6707318, Mar 16, 2004

Filed:

Mar 26, 2002

Appl. No.:

10/107740

Inventors:

Sudarshan Kumar - Fremont CA
Shahram Jamshidi - Cupertino CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 19096

US Classification:

326 98, 326 95

Abstract:

An entry latch to provide a dynamic signal at an output port in response to input static signals at a pulldown network, the pulldown network to conditionally discharge an internal node depending upon the input static signals, the entry latch comprising a pass transistor having a first source/drain connected to the output port and a second source/drain connected to a gate of a pullup pMOSFET, where the pullup pMOSFET turns ON only if the pulldown network does not turn ON during the evaluation phase.

US Patent:

6732136, May 4, 2004

Filed:

Dec 23, 1999

Appl. No.:

09/471201

Inventors:

Feng Chen - Portland OR
Thomas Fletcher - Portland OR
Shahram Jamshidi - Cupertino CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 750

US Classification:

708708

Abstract:

A small swing reducer circuit. An apparatus includes a first number of input terminals including at least two input terminals coupled to receive a differential small swing signal and a reducer circuit to generate differential, small swing sum and carry output signals based on data received via the input terminals.

US Patent:

6914848, Jul 5, 2005

Filed:

Jun 12, 2003

Appl. No.:

10/461562

Inventors:

Shahram Jamshidi - Cupertino CA, US
Sadarshan Kumar - Fremont CA, US
Sadhana Madhyastha - Los Altos CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C008/00

US Classification:

36523006, 365129

Abstract:

A memory, such as a register file or a cache, having stack pMOSFETs shared among its word line drivers, where a stack pMOSFET shared by a set of word line drivers has its drain connected to the sources of the pMOSFETs in the set or word line drivers, and were each stack pMOSFET is controlled by an enable signal so as to turn ON only if its corresponding set of word line drivers is enabled. The enable signal may be provided by a write or read enable port, or by the memory's address decoder. The stacked configuration of pMOSFETs significantly reduces sub-threshold leakage current in the word line drivers with very little penalty in performance.

US Patent:

6952118, Oct 4, 2005

Filed:

Dec 18, 2002

Appl. No.:

10/324307

Inventors:

Shahram Jamshidi - Cupertino CA, US
Sudarshan Kumar - Fremont CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K019/096

US Classification:

326 98, 326112

Abstract:

A gate-clocked domino circuit with reduced leakage current during an inactive state, where domino stages in the domino circuit have long channel length transistors in the pre-charge paths. During an inactive state, the domino stages are put in an evaluation state and are discharged.

US Patent:

7302652, Nov 27, 2007

Filed:

Mar 31, 2003

Appl. No.:

10/404937

Inventors:

Zhanping Chen - Portland OR, US
Lakshman Thiruvenkatachari - Santa Clara CA, US
Shahram Jamshidi - Cupertino CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716 4

Abstract:

Although there are a number of techniques available to reduce leakage current, there is still considerable room for improvement. Accordingly, the present inventors devised, among other things, an exemplary method which entails defining first and second leakage-reduction vectors for respective first and second portions of an integrated circuit, such as a microprocessor. The leakage-reduction vectors, in some embodiments, set the first and second portion to minimum leakage states and thus promise to reduce leakage power and extend battery life in devices that incorporate this technology.

US Patent:

7592840, Sep 22, 2009

Filed:

Nov 8, 2006

Appl. No.:

11/557913

Inventors:

Kin Yip Sit - Sunnyvale CA, US
Shahram Jamshidi - Cupertino CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 19/00

US Classification:

326112, 326 93, 326 95, 326 98

Abstract:

Some embodiments provide dynamic circuits with dynamic nodes that may float during a disable mode to reduce leakage.

US Patent:

55981143, Jan 28, 1997

Filed:

Sep 27, 1995

Appl. No.:

8/534487

Inventors:

Shahram Jamshidi - Santa Clara CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 19094
H03K 19084

US Classification:

326113

Abstract:

A multiplexer that comprises a first input buffer and a first pass gate coupled in series between a first data input and a common node and a second input buffer and a second pass gate coupled in series between a second data input and the common node. A biasing circuit is coupled to the common node and a supply voltage to bias the common node to the supply voltage when neither pass gate is switched on to pass data from its corresponding input buffer to the common node. An output buffer is coupled to the common node for outputting an output signal to a data output in response to a voltage of the common node.

US Patent:

56465580, Jul 8, 1997

Filed:

Sep 27, 1995

Appl. No.:

8/534598

Inventors:

Shahram Jamshidi - Santa Clara CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 19084
H03K 19094

US Classification:

326106

Abstract:

A multiplexing arrangement. The multiplexing arrangement comprises a set of data inputs wherein a first multiplexer is coupled to a first subset of the set of data inputs and a second multiplexer is coupled to a second subset of the set of data inputs. Only one of the first and second multiplexers is selected to pass one of the set of data inputs at any given time. A logic gate is coupled to the first and second data outputs, and the logic gate synthesizes an output signal for the multiplexing arrangement in response to values output by the first and second multiplexers such that the multiplexing arrangement operates as a single multiplexer. According to one embodiment, the multiplexer that is not selected to pass data has its output biased to a known state.