- Cupertino CA, US Jafar Savoj - Sunnyvale CA, US Brian S. Leibowitz - San Francisco CA, US Shah M. Sharif - San Jose CA, US
International Classification:
H03M 1/06
Abstract:
A serial data receiver circuit included in a computer system may include a front-end circuit, a sample circuit that includes multiple analog-to-digital converter circuits, and a recovery circuit. The front-end circuit may generate an equalized signal using multiple signals that encode a serial data stream of multiple data symbols. Based on a baud rate of the serial data stream, a determined number of the multiple analog-to-digital converter circuits sample, using a recovered clock signal, the equalized signal at the respective times to generate corresponding samples. The recovery circuit generates, using the samples, the recovered clock signal and recovered data symbols.
- Cupertino CA, US Shah M. Sharif - San Jose CA, US
International Classification:
G06F 1/3293 G06F 1/3287 G11C 5/14
Abstract:
A cross-domain power control circuit is disclosed. The circuit includes a first circuit branch having a first transistor coupled to a first supply voltage node and a second circuit branch having a second transistor coupled to the first supply voltage node. A third circuit branch is coupled between a second supply voltage node and a third supply voltage node. A second supply voltage conveyed on the second supply voltage node is less than a first supply voltage conveyed on the first supply voltage node. A fourth circuit branch is coupled between the first and third supply voltage nodes. In a first mode of operation, control circuitry causes the second supply voltage to be conveyed to the third supply voltage node. In a second mode of operation, the control circuitry causes the first supply voltage to be conveyed to the third supply voltage node.
Infinera Apr 2016 - Jan 2018
Principal Engineer
Apple Apr 2016 - Jan 2018
High Speed Adc Designer
Iq-Analog Corporation Feb 2013 - Feb 2016
Senior Principal Engineer
Skyworks Solutions, Inc. Dec 2011 - Feb 2013
Principal Design Engineer
Qualcomm Sep 2006 - Nov 2011
Analog Mixed Signal Ic Design Engineer
Education:
University of California, Los Angeles 2009 - 2013
Master of Science, Masters, Engineering
Arizona State University 1999 - 2000
Master of Science, Masters, Electrical Engineering
University of California
Skills:
Analog Mixed Signal Verilog Asic Rf Integrated Circuit Design Cellular Communications Cmos Analog Circuit Design Ic Cadence Virtuoso Soc Vlsi Circuit Design Semiconductors Eda Cadence Low Power Design Physical Design Spice Hardware Architecture Static Timing Analysis Pll Serdes Simulations Digital Signal Processors Integrated Circuits Radio Frequency
Skyworks Solutions, Inc. - Irvine,CA Dec 2011 - Feb 2013
Principal Design Engineer
Qualcomm - Greater San Diego Area Sep 2006 - Nov 2011
Analog Mixed Signal IC Design Engineer
Intel Corporation - Phoenix, Arizona Area Sep 2000 - Sep 2006
Analog Mixed Signal Design Engineer
Education:
University of California, Los Angeles 2009 - 2013
M.S, Engineering
Arizona State University 1999 - 2000
M.S, Electrical Engineering
2006 to 2011 Senior Mixed Signal IC Design EngineerQualcomm Inc
2006 to 2011Intel Corporation Chandler, AZ Sep 2000 to Sep 2006 Circuit Design EngineerEngineering and Technology Dhaka Aug 1998 to Dec 1998
Education:
University of California Los Angeles, CA Jan 2013 Masters in EngineeringArizona State University May 2000 Masters in Electrical EngineeringBangladesh Univ of Engg & Tech Jun 1998 B.S. in Electrical Engineeringclass in the top ranking university of the country Design of Yagi-Ada Antenna