Sandeep K Guliani from 109 Pembury Way, Folsom, CA 95630, age 61, Phone: 916-984-9667

Method And Apparatus For Low Voltage Sensing In Flash Memories
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US Patent:

6366497, Apr 2, 2002
Filed:

Mar 30, 2000
Appl. No.:

09/539725
Inventors:

Sandeep Guliani - Folsom CA
Chaitanya Rajguru - Folsom CA
Kedar Mangrulkar - Fair Oaks CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G11C 1606
US Classification:

36518521, 365210
Abstract:

In one embodiment, the invention is an apparatus. The apparatus includes a column load component and a current mirror coupled in parallel with the column load component. The column load component is capable of being coupled to a FLASH cell and a sense amplifier.

Sample And Hold Voltage Reference Source
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US Patent:

6434049, Aug 13, 2002
Filed:

Dec 29, 2000
Appl. No.:

09/753354
Inventors:

Ritesh Trivedi - Fair Oaks CA
Robert Baltar - Folsom CA
Mark Bauer - Placerville CA
Sandeep Guliani - Folsom CA
Balaji Srinivasan - Fair Oaks CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G11C 1606
US Classification:

3651852, 36518518, 36518909
Abstract:

An apparatus and method are disclosed for providing a sample and hold voltage reference for non-volatile memory. According to one embodiment, the sample and hold voltage reference produces a reference voltage for a drain bias circuit of a memory cell.

Vpx Bank Architecture
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US Patent:

6434073, Aug 13, 2002
Filed:

Aug 7, 2001
Appl. No.:

09/924888
Inventors:

Sandeep K. Guliani - Folsom CA
Rajesh Sundaram - Fair Oaks CA
Mase J. Taub - Elk Grove CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G11C 702
US Classification:

365210, 36523003, 36523006
Abstract:

A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank including memory cells. The banks are provided with a supply voltage.

Vpx Bank Architecture
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US Patent:

6459645, Oct 1, 2002
Filed:

Sep 30, 1999
Appl. No.:

09/410493
Inventors:

Sandeep K. Guliani - Folsom CA
Rajesh Sundaram - Fair Oaks CA
Mase J. Taub - Elk Grove CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G11C 800
US Classification:

36523003, 36518511, 36523006
Abstract:

A method and apparatus to segment a programmable non-volatile memory array into at least two banks. The banks include memory cells. Each bank in the at least two banks is provided with a local programming voltage. Each local programming voltage is independent of the other local programming voltages supplied to the other banks.

Vpx Bank Architecture
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US Patent:

6463004, Oct 8, 2002
Filed:

Aug 7, 2001
Appl. No.:

09/924922
Inventors:

Sandeep K. Guliani - Folsom CA
Rajesh Sundaram - Fair Oaks CA
Mase J. Taub - Elk Grove CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G11C 800
US Classification:

36523003, 36518511, 36523006
Abstract:

A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank including memory cells. The banks are provided with a supply voltage.

Local Sensing Of Non-Volatile Memory
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US Patent:

6477086, Nov 5, 2002
Filed:

Dec 29, 2000
Appl. No.:

09/752936
Inventors:

Ritesh Trivedi - Fair Oaks CA
Mark Bauer - Placerville CA
Sandeep Guliani - Folsom CA
Balaji Srinivasan - Fair Oaks CA
Kerry Tedrow - Folsom CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G11C 1606
US Classification:

36518521, 36518522, 36518511
Abstract:

According to the invention, an apparatus and method are disclosed for sensing the contents of non-volatile memory. According to one embodiment, a set of local sensing circuits is used to read the logical values stored in memory cells contained within a partition of a non-volatile memory device.

Drain Bias For Non-Volatile Memory
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US Patent:

6535423, Mar 18, 2003
Filed:

Dec 29, 2000
Appl. No.:

09/752370
Inventors:

Ritesh Trivedi - Fair Oaks CA
Robert Baltar - Folsom CA
Mark Bauer - Placerville CA
Sandeep Guliani - Folsom CA
Balaji Srinivasan - Fair Oaks CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G11C 700
US Classification:

36518518, 3651852, 36518521, 36518524
Abstract:

An apparatus and method are disclosed for providing drain bias for non-volatile memory. According to one embodiment, the drain bias is provided utilizing a drain bias circuit that is referenced by a static voltage reference.

Load For Non-Volatile Memory Drain Bias
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US Patent:

6570789, May 27, 2003
Filed:

Dec 29, 2000
Appl. No.:

09/752535
Inventors:

Ritesh Trivedi - Fair Oaks CA
Robert Baltar - Folsom CA
Mark Bauer - Placerville CA
Sandeep Guliani - Folsom CA
Balaji Srinivasan - Fair Oaks CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G11C 1606
US Classification:

3651852, 36518521, 36518518
Abstract:

An apparatus is disclosed for providing a load for a non-volatile memory drain bias circuit. Under an embodiment, a load for a non-volatile memory drain bias circuit comprises a column load and a current mirror, a reference voltage for the current mirror being a sample and hold voltage reference. The column load and the current mirror are coupled to a cascode device.

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Location:

Folsom, CA

Industry:

Semiconductors

Work:

Intel Corporation
Principal Engineer

Skills:

Marketing
Semiconductors
Quality Assurance
Software

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Sandeep K Guliani