Samir Aboulhouda from Portola Valley, CA, age 61

Fiber Optic Link, A Transceiver For Use In The Link, And Methods For Designing And Constructing Fiber Optic Links And Transceivers
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US Patent:

20090103927, Apr 23, 2009
Filed:

Oct 17, 2007
Appl. No.:

11/873550
Inventors:

David George Cunningham - Fort Collins CO, US
Ronald Kaneshiro - Los Altos CA, US
Samir Aboulhouda - Cupertino CA, US
International Classification:

H04B 10/00
US Classification:

398139
Abstract:

A fiber optic link is provided that uses a relatively low-cost transceiver that incorporates relatively inexpensive low bandwidth optical and electrical components to achieve high data rate operations. The data rate of the fiber optic link can be greater than the data rate of the laser of the transceiver provided the laser meets certain noise requirements; in particular, the relative intensity noise (RIN) of the laser must be low enough to ensure low bit error rate (BER) operation of the link.

High-Speed Optical Fiber Link And A Method For Communicating Optical Data Signals
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US Patent:

20130287394, Oct 31, 2013
Filed:

Apr 30, 2012
Appl. No.:

13/460833
Inventors:

Faouzi Chaahoub - Cupertino CA, US
Georgios Asmanis - Lake Forest CA, US
Samir Aboulhouda - Cupertino CA, US
Michael A. Robinson - Fremont CA, US
International Classification:

H04B 10/14
H04J 14/00
US Classification:

398 43, 398139, 398136
Abstract:

An optical communications system and method at least doubles the data rate of the optical fiber link without requiring a redesign of the backplane ASIC. This is made possible in part through the incorporation of at least one gearbox integrated circuit (IC) is incorporated into the system that is compatible with the current ASIC design. The gearbox IC receives N lanes of electrical data signals from the ASIC, with each electrical data signal having a data rate of X Gbps, and outputs N/2 lanes of electrical data signals, with each electrical data signal having a data rate of 2X Gbps. The high-speed optical transceiver module receives the N/2 electrical data signals output from the gearbox IC and produces N/2 respective optical data signals having a data rate of 2X Gbps for transmission over the optical fiber link.

Method And Apparatus For Performing Data Rate Conversion And Phase Alignment
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US Patent:

20140010546, Jan 9, 2014
Filed:

Jul 9, 2012
Appl. No.:

13/544199
Inventors:

Faouzi Chaahoub - San Jose CA, US
Georgios Asmanis - Lake Forest CA, US
Samir Aboulhouda - Cupertino CA, US
Michael A. Robinson - Fremont CA, US
Ravi T. Kotamraju - Sunnyvale CA, US
Assignee:

AVAGO TECHNOLOGIES FIBER IP (SINGAPORE) PTE. LTD. - SINGAPORE
International Classification:

H04B 10/00
US Classification:

398116
Abstract:

A gearbox IC is incorporated into an optical communications system to enable an optical link that incorporates the system to achieve data rates that are at least double that which are currently achievable in optical links. The gearbox IC performs data rate conversion and phase alignment. In the transmit direction, the gearbox IC receives N lanes of electrical data signals having a data rate of X Gbps and outputs N/2 lanes of electrical data signals having a data rate of 2X Gbps. In the receive direction, the gearbox IC receives N/2 electrical data signals having a data rate of 2X Gbps and converts the N/2 electrical data signals into N electrical data signals having a data rate of X.

Integrated Circuit Incorporating A Low Power Data Retiming Circuit
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US Patent:

20160359611, Dec 8, 2016
Filed:

Jun 2, 2015
Appl. No.:

14/728575
Inventors:

- Singapore, SG
Samir Aboulhouda - Portola Valley CA, US
Ramana Murty Malladi - Williston VT, US
International Classification:

H04L 7/00
H04L 7/033
Abstract:

A low power data retiming circuit incorporates CMOS components in certain sections that operate at a lower frequency in comparison to certain other sections that use components based on bipolar technology for operating at a relatively higher frequency. The data retiming circuit includes a clock recovery circuit wherein a voltage controlled oscillator provides a recovered clock to a clock generator circuit for generating a latched clock that is provided to a phase detector and a data serializer. The data serializer operates as a synchronous multiplexer for generating a retimed data output signal from a pair of latched data input signals. The phase detector and the data serializer operate in a half-rate mode wherein high and low voltage levels of the latched clock are used for clocking data. The half-rate mode of operation permits the use of a clock frequency that is half that of an input data rate.

Rate-Adaptive Equalizer That Automatically Initializes Itself Based On Detected Channel Conditions, And A Method
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US Patent:

20150117510, Apr 30, 2015
Filed:

Oct 31, 2013
Appl. No.:

14/069338
Inventors:

- Singapore, SG
Georgios Asmanis - Lake Forest CA, US
Sriramkumar Sundararaman - Belmont CA, US
Samir Aboulhouda - Cupertino CA, US
Assignee:

Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore
International Classification:

H04L 25/03
US Classification:

375233
Abstract:

A rate-adaptive equalizer automatically initializes its tap coefficients to values. During an initialization process, a linear search algorithm is performed that sweeps the tap coefficients through different combinations of tap coefficients while assessing information about an eye associated with an input signal received over a communications channel. When the eye information indicates that the eye is open, the current tap coefficients are selected as the initial tap coefficients to be used at the beginning of the main adaptation algorithm.

Adaptive Equalizer
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US Patent:

20150049797, Feb 19, 2015
Filed:

Aug 17, 2013
Appl. No.:

13/969534
Inventors:

- Singapore, SG
Faouzi Chaahoub - San Jose CA, US
Samir Aboulhouda - Cupertino CA, US
Sriramkumar Sundararaman - Belmont CA, US
Ajay Kumar Yadav - Belmont CA, US
Assignee:

Avago Technologies General IP (Singapore) Pte. Ltd - Singapore
International Classification:

H04L 25/03
US Classification:

375232
Abstract:

An equalizer that includes equalizer circuitry, a mean squared error (MSE) system, and adaptive control logic includes features that inhibit undesirable convergence to local minima.