Ruchika R Kharwar
age ~48
from Plano, TX
- Also known as:
-
- Ruchika R Khawar
- Phone and address:
- 3605 Dewberry Ct, Plano, TX 75025
Ruchika Kharwar Phones & Addresses
- 3605 Dewberry Ct, Plano, TX 75025
- Mc Kinney, TX
- 4015 Candle Cove Ct, Sugar Land, TX 77479
- 12250 S Kirkwood Rd #22, Stafford, TX 77477
Work
-
Company:Texas instrumentsJul 2000
-
Position:Software experience
Education
-
School / High School:Sardar patel college of engineering- Mumbai, MaharashtraJan 1996
-
Specialities:BE in Computer engineering
Skills
DSP BIOS • Linux • C++ • Assembly language (TMS320C54x • Applications • TMS320C55x • TMS320C64x+) • Code Composer Studio(eclipse based) • SystemC • RTL Simulators • QuickTurn • TMS320C54x • TMS320C55x • TMS320C64x+ (TMS320C6455) • Universal Serial Bus (USB) • USB2.0 • USB3.0 Superspeed host • Universal Asynchronous Receiver Transmit... • Inter Integrated Circuit (I2C) • Enhanced Direct Memory Access (EDMA) • TI internal Bus protocols (Common Bus Ar... • Open Core Protocol (OCP Bus) • Debgger usage: JTAG • Lauterbach • Waveform analysis
Languages
English • Hindi
Interests
Children • Design • Education • Art • Science and Technology • Running • Swimming
Industries
Semiconductors
Resumes
Ruchika Kharwar
view sourceLocation:
4451 Posada Dr, Dallas, TX 75211
Industry:
Semiconductors
Work:
Red Hat
Cloud Success Architect
Home Office
Embedded System Engineer, Developer
Startup Experience Jul 1, 2013 - Mar 1, 2015
System and Validation Engineer
Texas Instruments Jul 1, 2011 - Jul 1, 2013
Systems Engineer: Software
Texas Instruments Feb 2009 - Sep 2011
Systems Engineer: System on Chip Architecture
Cloud Success Architect
Home Office
Embedded System Engineer, Developer
Startup Experience Jul 1, 2013 - Mar 1, 2015
System and Validation Engineer
Texas Instruments Jul 1, 2011 - Jul 1, 2013
Systems Engineer: Software
Texas Instruments Feb 2009 - Sep 2011
Systems Engineer: System on Chip Architecture
Education:
Sardar Patel College of Engineering Andheri (West) Mumbai 400 058 1996 - 2000
Bachelor of Engineering, Bachelors, Computer Engineering D.g. Ruparel College of Science 1996 - 1998
Bachelor of Engineering, Bachelors, Computer Engineering D.g. Ruparel College of Science 1996 - 1998
Skills:
Embedded Software
C64X+
Computer Architecture
Linux
C
Debugging
Soc Architecture Analysis
Perl
Start Ups
Arm
Processors
Bus Dev
Debuggers
Verilog
Ceph
Usb
Design Specifications
Linux Kernel
Embedded Linux
Embedded Systems
Testing
Embedded C
Embedded Operating Systems
Soc
C++
Dsp
Digital Signal Processing
Python
Bus Protocols
Semiconductors
Firmware
Emerging Technologies
Digital Signal Processors
Software Development
Device Drivers
Rtos
I2C
Analysis
Ic
C64X+
Computer Architecture
Linux
C
Debugging
Soc Architecture Analysis
Perl
Start Ups
Arm
Processors
Bus Dev
Debuggers
Verilog
Ceph
Usb
Design Specifications
Linux Kernel
Embedded Linux
Embedded Systems
Testing
Embedded C
Embedded Operating Systems
Soc
C++
Dsp
Digital Signal Processing
Python
Bus Protocols
Semiconductors
Firmware
Emerging Technologies
Digital Signal Processors
Software Development
Device Drivers
Rtos
I2C
Analysis
Ic
Interests:
Children
Design
Education
Art
Science and Technology
Running
Swimming
Design
Education
Art
Science and Technology
Running
Swimming
Languages:
English
Hindi
Hindi
Ruchika Kharwar Plano, TX
view sourceWork:
Texas Instruments
Jul 2000 to 2000
Software Experience Texas Instruments
Jul 2000 to 2000
SoC Architecture Skills Texas Instruments
Jul 2000 to 2000
Debug and Tools Skills Texas Instruments
Jul 2000 to 2000
Management Skills
Jul 2000 to 2000
Software Experience Texas Instruments
Jul 2000 to 2000
SoC Architecture Skills Texas Instruments
Jul 2000 to 2000
Debug and Tools Skills Texas Instruments
Jul 2000 to 2000
Management Skills
Education:
Sardar patel college of engineering
Mumbai, Maharashtra
Jan 1996 to Jan 2000
BE in Computer engineering
Mumbai, Maharashtra
Jan 1996 to Jan 2000
BE in Computer engineering
Skills:
DSP BIOS, Linux,, C++, Assembly language (TMS320C54x, Applications ,TMS320C55x, TMS320C64x+), Code Composer Studio(eclipse based), SystemC, RTL Simulators, QuickTurn, TMS320C54x, TMS320C55x, TMS320C64x+ (TMS320C6455), Universal Serial Bus (USB), USB2.0, USB3.0 Superspeed host, Universal Asynchronous Receiver Transmitter (UART),Inter Integrated Circuit (I2C), Enhanced Direct Memory Access (EDMA), TI internal Bus protocols (Common Bus Architecture), Open Core Protocol (OCP Bus), Debgger usage: JTAG, Lauterbach, Waveform analysis
Youtube
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Ruchika Kharwar Google+
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