Roderick A Augur from 2 Cygnet Cir, Saratoga Springs, NY 12866, age 65, Phone: 518-886-9622

Us Patents

Semiconductor Device With Electrically Biased Die Edge Seal
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US Patent:

7235867, Jun 26, 2007
Filed:

Nov 1, 2004
Appl. No.:

10/976876
Inventors:

Roderick A. Augur - Hopewell Junction NY, US
Steven C. Avanzino - Cupertino CA, US
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

H01L 23/552
H01L 23/04
US Classification:

257659, 257660, 257730, 257E23193
Abstract:

A die seal arrangement and method for making the same negatively biases the die edge seal of a die by connecting the die edge seal to a source of negative electrical potential, with respect to electrical ground. The die edge seal, made of copper, for example, has its oxidation reaction potential shifted to a region which is energetically unfavorable. This significantly retards or eliminates oxidation of the copper die edge seal at circuit operation temperature, thereby maintain the integrity and functionality of the die edge seal to protect active circuitry on the die, even when the die edge seal is exposed to moisture and air.

Methods Relating To Capacitive Monitoring Of Layer Characteristics During Back End-Of The-Line Processing
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US Patent:

8241927, Aug 14, 2012
Filed:

Oct 14, 2009
Appl. No.:

12/579216
Inventors:

Jihong Choi - Fishkill NY, US
Yongsik Moon - Paramus NJ, US
Roderick Augur - Hopewell Junction NY, US
Eden Zielinski - Wappingers Falls NY, US
Assignee:

Global Foundries, Inc. - Grand Cayman
International Classification:

H01L 21/66
US Classification:

438 17, 257529, 257773, 257E21531, 257774, 438667
Abstract:

Methods are provided that relate to the capacitive monitoring of characteristic pertaining to layer formed during the back end-of-the-line (BEOL) processing of a semiconductor device. In one embodiment, a method includes the steps of forming a first capacitor array including first and second overlying contacts each formed in a different one of the plurality of BEOL layers, measuring the interlayer capacitance between the first and second overlying contacts, and converting the measured interlayer capacitance to a distance between the first and second overlying contacts.

Integrated Circuits Having Backside Test Structures And Methods For The Fabrication Thereof
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US Patent:

8349734, Jan 8, 2013
Filed:

Apr 7, 2010
Appl. No.:

12/755983
Inventors:

Roderick Augur - Hopewell Junction NY, US
Assignee:

GLOBALFOUNDRIES, Inc. - Grand Cayman
International Classification:

H01L 21/44
H01L 29/40
US Classification:

438667, 257621, 257E21597, 257E23011
Abstract:

Embodiments of a method for fabricating an integrated circuit having a backside test structure are provided. In one embodiment, the method includes the steps of providing a semiconductor substrate, forming at least one Through-Silicon-Via (TSV) through the semiconductor substrate, forming a backside probe pad over the backside of the semiconductor substrate and electrically coupled to the at least one TSV, and forming a frontside bondpad over the frontside of the semiconductor substrate. The frontside bondpad is electrically coupled to the backside probe pad by the at least one TSV.

Integrated Circuits With Improved Interconnect Reliability Using An Insulating Monolayer And Methods For Fabricating Same
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US Patent:

20130221524, Aug 29, 2013
Filed:

Feb 29, 2012
Appl. No.:

13/407815
Inventors:

Roderick A. Augur - Hopewell Junction NY, US
Errol T. Ryan - Clifton Park NY, US
Assignee:

GLOBALFOUNDRIES INC. - Grand Cayman
International Classification:

H01L 23/48
H01L 21/56
US Classification:

257741, 257734, 438107, 257E2301, 257E21502
Abstract:

Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes an interlayer dielectric material having a top surface and overlying semiconductor devices formed on a semiconductor substrate. The integrated circuit includes a metal interconnect formed in the interlayer dielectric material. The metal interconnect includes an upper surface to which an insulating monolayer is bonded. The integrated circuit further includes a dielectric cap that overlies the top surface of the interlayer dielectric material and encapsulates the insulating monolayer.

System And Method To Improve Uniformity Of Ultraviolet Energy Application And Method For Making The Same
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US Patent:

7081638, Jul 25, 2006
Filed:

Oct 25, 2004
Appl. No.:

10/971018
Inventors:

Roderick A. Augur - Hopewell Junction NY, US
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

A61N 5/06
G01J 3/10
H05G 2/00
US Classification:

250504R, 250504 R
Abstract:

A UV system, such as used in UV curing of dielectric material, for example, and a method of making the same, has a reflector and a localized UV source positioned at an optical center of the reflector. The window separates the UV source from a work piece. The UV source is on a first side of the window and the work piece is on a second side of the window. A partially reflecting mirror is provided on the first side of the window. The partially reflecting mirror, with the reflector and localized UV source, provides for a maximum amount of UV energy to be provided in a uniformly distributed manner across the plane of the window to the work piece.

Wavelength-Division Multiplexing Filters Including Assisted Coupling Regions
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US Patent:

20220299706, Sep 22, 2022
Filed:

Mar 16, 2021
Appl. No.:

17/202729
Inventors:

- Santa Clara CA, US
- Abu Dhabi, AE
Roderick A. Augur - Saratoga Springs NY, US
Marios Papadovasilakis - Dubai, AE
Sujith Chandran - Abu Dhabi, AE
Jaime Viegas - Abu Dhabi, AE
Yonas Gebregiorgis - Abu Dhabi, AE
International Classification:

G02B 6/12
G02B 6/122
G02B 6/13
G02B 6/125
Abstract:

Structures for a wavelength-division multiplexing filter and methods of forming a structure for a wavelength-division multiplexing filter. A waveguide core of the wavelength-division multiplexing filter includes a first bend having a first curvature and a second bend having a second curvature different than the first curvature. The structure further includes a waveguide core region having a first end surface, a second end surface, and a bend arranged between the first and second end surfaces. The bend is positioned over the first bend of the waveguide core in an overlapping relationship.

Perforated Wavelength-Division Multiplexing Filters
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US Patent:

20220252784, Aug 11, 2022
Filed:

Feb 8, 2021
Appl. No.:

17/170203
Inventors:

- Santa Clara CA, US
Yusheng Bian - Ballston Lake NY, US
Michal Rakowski - Ballston Lake NY, US
Won Suk Lee - Malta NY, US
Asif J. Chowdhury - Clifton Park NY, US
Roderick A. Augur - Saratoga Springs NY, US
International Classification:

G02B 6/12
G02B 6/13
G02B 1/00
Abstract:

Structures for a wavelength-division multiplexing filter and methods of forming a structure for a wavelength-division multiplexing filter. The structure includes a first slab having a first perimeter, a first waveguide core coupled to the first slab, and a plurality of second waveguide cores coupled to the first slab. A second slab is positioned to overlap with the first slab. The second slab includes a second perimeter and openings that are distributed inside the second perimeter. The openings of the second slab penetrate through the second slab.

Metamaterial Edge Couplers In The Back-End-Of-Line Stack Of A Photonics Chip
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US Patent:

20220252785, Aug 11, 2022
Filed:

Feb 11, 2021
Appl. No.:

17/173639
Inventors:

- Santa Clara CA, US
Roderick A. Augur - Saratoga Springs NY, US
Kenneth J. Giewont - Hopewell Junction NY, US
Karen Nummy - Newburgh NY, US
International Classification:

G02B 6/122
F21V 8/00
G02B 6/14
Abstract:

Structures for an edge coupler and methods of forming a structure for an edge coupler. The structure includes a waveguide core over a dielectric layer, and a back-end-of-line stack over the waveguide core and the dielectric layer. The back-end-of-line stack includes an interlayer dielectric layer, a side edge, a first feature, a second feature, and a third feature laterally arranged between the first feature and the second feature. The first feature, the second feature, and the third feature are positioned on the interlayer dielectric layer adjacent to the side edge, and the third feature has an overlapping relationship with a tapered section of the waveguide core.