Robert Joseph Horning

US Patent:

6457105, Sep 24, 2002

Filed:

Jan 15, 1999

Appl. No.:

09/232505

Inventors:

Thomas V Spencer - Ft Collins CO
Robert J Horning - Ft Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1200

US Classification:

711136, 711160

Abstract:

The present invention is generally directed to a system and method for providing improved memory management in an asynchronous I/O cache memory. The method includes the steps of identifying a request for data from the system memory by a requesting device that is in communication with the system memory via an I/O bus. Then the method controls the communication of data from the system memory into the cache memory. The method further includes the step of communicating the data from the cache memory to the requesting device, and immediately after communicating the data to the requesting device, the method discards the data from the cache memory. In accordance with the preferred embodiment, the method flushes data from the I/O cache line at a time. Therefore, when a given cache line of data is flushed from the cache after the last data byte of the cache line is communicated out to the requesting device.

US Patent:

6542968, Apr 1, 2003

Filed:

Jan 15, 1999

Appl. No.:

09/232293

Inventors:

Thomas V Spencer - Ft Collins CO
Robert J Horning - Ft Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1200

US Classification:

711137, 711154

Abstract:

The present invention is generally directed to a system and method for fetching data from system memory to a device in communication with the system over a PCI bus, via an I/O cache. Broadly, the present invention may be viewed as a novel way to communicate certain fetching hints; namely, hints that specify certain qualities about the data that is to be fetched from the system memory. In operation, the I/O cache may use such hints to more effectively manage the data that passes through it. As simply one example, if, based upon the hints, the controller for the I/O cache knew (or assumed) that the data being fetched was ATM data, then it would also know (based upon the nature of ATM data) that precisely a forty-eight byte data payload was to be sent to the requesting device, and the I/O cache could pre-fetch precisely this amount of data (typically one or two cache lines). In accordance with one aspect of the invention, such a system includes an input/output (I/O) cache memory interposed between the system memory and the PCI bus, wherein the cache memory has internal memory space in the form of a plurality of data lines within the cache memory. The system further includes a plurality of registers for each PCI master that are configured to define fetching criteria.

US Patent:

6772295, Aug 3, 2004

Filed:

Dec 17, 2002

Appl. No.:

10/322222

Inventors:

Thomas V. Spencer - Ft Collins CO
Robert J. Horning - Ft Collins CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1200

US Classification:

711137

Abstract:

The present invention is generally directed to a system and method for fetching data from system memory to a device in communication with the system over a PCI bus, via an I/O cache. Broadly, the present invention may be viewed as a novel way to communicate certain fetching hints; namely, hints that specify certain qualities about the data that is to be fetched from the system memory. In operation, the I/O cache may use such hints to more effectively manage the data that passes through it. As simply one example, if, based upon the hints, the controller for the I/O cache knew (or assumed) that the data being fetched was ATM data, then it would also know (based upon the nature of ATM data) that precisely a forty-eight byte data payload was to be sent to the requesting device, and the I/O cache could pre-fetch precisely this amount of data (typically one or two cache lines). In accordance with one-aspect of the invention, such a system includes an input/output (I/O) cache memory interposed between the system memory and the PCI bus, wherein the cache memory has internal memory space in the form of a plurality of data lines within the cache memory. The system further includes a plurality of registers for each PCI master that are configured to define fetching criteria.

US Patent:

20110289337, Nov 24, 2011

Filed:

Feb 27, 2009

Appl. No.:

13/147429

Inventors:

Eugene M. Dvoskin - Broomfield CO, US
Noel D. Scott - Fort Collins CO, US
Robert J. Horning - Fort Collins CO, US

International Classification:

G06F 1/28

US Classification:

713340

Abstract:

Reporting electrical current to a processor. At least some of the illustrative embodiments are methods including providing operational power to a processor at a voltage indicated by the processor of a computer system, measuring electrical current actually drawn by the processor, and reporting to the processor a value of electrical current drawn by the processor. The value of electrical current reported different than the electrical current actually drawn by more than a measurement error of measuring the electrical current actually drawn.

US Patent:

20120260015, Oct 11, 2012

Filed:

Apr 7, 2011

Appl. No.:

13/082282

Inventors:

Raphael Gay - Fort Collins CO, US
Robert J. Horning - Fort Collins CO, US
Robert Bohl - Fort Collins CO, US
Brooke Melinda O'Dell Loader - Fort Collins CO, US

International Classification:

G06F 13/14

US Classification:

710301

Abstract:

Peripheral Component Interconnect Express (“PCIe”) Port bifurcation systems and methods are provided. An illustrative PCIe port bifurcation card can include: a PCIe interface and a plurality of PCIe devices, each independently coupled to the interface via an unswitched connection. The card can further include a read only memory (ROM) coupled to the interface, the ROM can include bifurcation data. A clocking signal replicator can be coupled to the interface to: replicate a reference clock signal received via the interface and provide the replicated reference dock signal to each of the plurality of PCIe devices.

US Patent:

20130173901, Jul 4, 2013

Filed:

Nov 1, 2010

Appl. No.:

13/821506

Inventors:

Raphael Gay - Fort Collins CO, US
Robert J. Horning - Fort Collins CO, US

International Classification:

G06F 9/44

US Classification:

713 2

Abstract:

Multi-processor computer systems and methods are provided. A multi-processor computer system can include a plurality of communicatively coupled processors (), each coupled to a common motherboard () and each associated with a memory (). The system can include a boot code () executable from at least one of a standard mode and an independent mode. The plurality of communicatively coupled processors can execute one instance of the boot code in standard mode and at least a portion of the plurality of communicatively coupled processors can execute one instance of the boot code in independent mode.

US Patent:

62790811, Aug 21, 2001

Filed:

Dec 22, 1998

Appl. No.:

9/218226

Inventors:

Thomas V Spencer - Ft Collins CO
Robert J Horning - Ft Collins CO
Monish S Shah - San Jose CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1200

US Classification:

711137

Abstract:

The present invention is generally directed to a system and method for fetching data from a system memory to an ATM card. The method includes the steps of receiving a request (via a PCI bus) to fetch data from memory, and identifying the request as an ATM request. The method then determines, based on the start address, the number of cache lines that will be implicated by the fetch. Then, the method automatically fetches the appropriate number of cache lines into the cache, and then passes the data to the ATM card, via the PCI bus. In accordance with another aspect of the present invention, a system is provided for fetching data from memory for an ATM card. Broadly, the system includes a system memory for data storage and a cache memory for providing high-speed (retrieval) temporary storage of data, the cache memory being disposed in communication with the system memory via a high-speed system bus. The system further includes a PCI bus in communication with the cache memory via an input/output (I/O) bus. A first mechanism is configured to identify a fetch for data from memory to the PCI bus by an ATM card.

US Patent:

54169186, May 16, 1995

Filed:

Jan 27, 1994

Appl. No.:

8/187264

Inventors:

Craig A. Gleason - Fort Collins CO
Robert J. Horning - Fort Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 104
G06F 110

US Classification:

395550

Abstract:

A low skew interface system for enabling an ASIC chip's receivers to latch information from one or more buses. The interface comprises a driver circuit connected to an internal clock of the chip for generating another clock signal with phase different from the phase of the internal clock. A delay element is located off the chip and connected to the driver circuit for delaying the clock signal, thereby generating a latch clock signal. The latch clock signal is sent back on-chip to enable the receivers to transfer information from one of the buses to the chip.