Robert C Ghest

US Patent:

41539389, May 8, 1979

Filed:

Aug 18, 1977

Appl. No.:

5/825648

Inventors:

Robert C. Ghest - Saratoga CA
John M. Birkner - Santa Clara CA

Assignee:

Monolithic Memories Inc. - Sunnyvale CA

International Classification:

G06F 752

US Classification:

364760

Abstract:

This disclosure relates to a high speed combinatorial 8 by 8 digital multiplier suitable for implementation on a single semiconductor chip including an encoder for implementing the Modified Booth Algorithm to encode the eight multiplier digits. The encoder includes five subsections which generate a plurality of control signals. Each of the plurality of control signals is inputted into a separate one of five multiplexor circuits each of which also receives inputs representative of eight multiplicand bits in accordance with implementation of the Modified Booth Algorithm. Each of the five multiplexer circuits provides a plurality of outputs, each of the pluralities of outputs representing a separate partial product of the multiplier and multiplicand inputs. The partial products are inputted to an array of carry-save adders. The final stage of the adder network includes a carry-look-ahead adder which produces sixteen outputs which represent the product of the multiplier and the multiplicand.

US Patent:

42388333, Dec 9, 1980

Filed:

Mar 28, 1979

Appl. No.:

6/024540

Inventors:

Robert C. Ghest - Saratoga CA
John M. Birkner - Sunnyvale CA
Shlomo Waser - Sunnyvale CA
Hua T. Chua - Cupertino CA

Assignee:

Monolithic Memories, Inc. - Sunnyvale CA

International Classification:

G06F 752

US Classification:

364760

Abstract:

A bus organized 16. times. 16 (or 8. times. 8) high-speed digital bus-organized multiplier/divider for high-speed, low-power operation is implemented on a single semiconductor chip. Four working registers each of 16 (or 8) bits are used in the system. These registers are a multiplier register, a multiplicand and divisor register, a first accumulator register for storing the least significant half of a double length product after a multiplication of the remainder after a division operation, and a second accumulator register which stores the most significant half of the product after a multiplication or the quotient after a division operation. A decoder is connected to the multiplicand and multiplier registers to implement the Modified Booth Algorithm and to encode the 16 (or 8) multiplier digits. The system operates to shift the multiplier number through the multiplier register to a position where the Modified Booth Algorithm encoding takes place. The Modified Booth encoder then controls the operation of multiplexer circuits to which the outputs of the multiplicand register are applied to produce successive partial products.