Richard A Wachnik

US Patent:

6417572, Jul 9, 2002

Filed:

Jul 16, 1999

Appl. No.:

09/354592

Inventors:

Dureseti Chidambarrao - Weston CT
Ronald G. Filippi - Wappingers Falls NY
Robert Rosenberg - Cortlandt Manor NY
Thomas M. Shaw - Peekskill NY
Timothy D. Sullivan - Underhill VT
Richard A. Wachnik - Mount Kisco NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348

US Classification:

257773, 257775, 257765

Abstract:

A process for producing a multi-level semiconductor device having metal interconnections with insulating passivation layers and the product produced thereby. The product and process improve the resistance of the metallization interconnections to extrusion-short electromigration failures by preventing the insulating passivation layers from cracking. The product and process also reduce the level of resistance saturation or the maximum resistance shift caused by electromigration. By replacing wide-line metallization interconnection conducting lines surrounded by insulating passivation layers with two or more narrow, parallel conducting lines having aspect ratios less than or equal to unity with passivation layers located in between, the incidence of passivation cracking and extrusion-short failures is reduced. The process is especially suited for use in multi-level wiring structures in which the wiring levels have diffusion barriers between the wiring levels caused by redundant metallization layers, interlevel connections, or both.

US Patent:

6531759, Mar 11, 2003

Filed:

Feb 6, 2001

Appl. No.:

09/777540

Inventors:

Richard A. Wachnik - Mount Kisco NY
Charles R. Davis - Fishkill NY
Theodore H. Zabel - Yorktown Heights NY
Phillip J. Restle - Katonah NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23552

US Classification:

257659, 257660, 257642, 257643, 438 82, 438725

Abstract:

An integrated circuit, comprising: a semiconductor substrate, a plurality of last metal conductors disposed above said substrate, a bottom metallic layer disposed on said last metal conductors, a top metallic layer, and an alpha absorber disposed between said bottom and top metallic layers, said alpha absorber consisting essentially of a high-purity metal which is an alpha-particle absorber. The metal is, for example, of Ta, W, Re, Os or Ir.

US Patent:

7217978, May 15, 2007

Filed:

Jan 19, 2005

Appl. No.:

11/038593

Inventors:

Rajiv V. Joshi - Yorktown Heights NY, US
Richard Andre Wachnik - Mount Kisco NY, US
Yue Tan - Fishkill NY, US
Kerry Bernstein - Underhill VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/01

US Classification:

257351, 257E27098

Abstract:

The present invention generally concerns fabrication methods and device architectures for use in memory circuits, and more particularly concerns hybrid silicon-on-insulator (SOI) and bulk architectures for use in memory circuits. Once aspect of the invention concerns CMOS SRAM cell architectures where at least one pair of adjacent NFETs in an SRAM cell have body regions linked by a leakage path diffusion region positioned beneath shallow source/drain diffusions, where the leakage path diffusion region extends from the bottom of the source/drain diffusion to the buried oxide layer, and at least one pair of NFETs from adjacent SRAM cells which have body regions linked by a similar leakage path diffusion region beneath adjacent source/drain diffusions. Another aspect of this invention concerns a microprocessor fabricated on an hybrid orientation substrate where the logic portion of the circuit has NFETs fabricated in (100) crystal orientation SOI silicon regions with floating body regions and PFETs fabricated in (110) crystal orientation bulk silicon regions; and where the SRAM memory portion has NFETs fabricated in (100) crystal orientation SOI silicon regions with body regions linked by leakage path diffusion regions beneath shallow source/drain diffusions and PFETs fabricated in (110) crystal orientation silicon regions.

US Patent:

7224063, May 29, 2007

Filed:

Jun 1, 2001

Appl. No.:

09/871883

Inventors:

Birendra N. Agarwala - Hopewell Junction NY, US
Eric M. Coker - Burlington VT, US
Anthony Correale, Jr. - Raleigh NC, US
Hazara S. Rathore - Stormville NY, US
Timothy D. Sullivan - Underhill VT, US
Richard A. Wachnik - Mount Kisco NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/52

US Classification:

257758, 257753, 257767, 257773, 257E23142, 257E23145

Abstract:

An interconnect structure, comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.

US Patent:

7260810, Aug 21, 2007

Filed:

Oct 16, 2003

Appl. No.:

10/687475

Inventors:

Giovanni Fiorenza - Pomona NY, US
Xiao Hu Liu - Croton-on-Hudson NY, US
Conal Eugene Murray - Yorktown Heights NY, US
Gregory Allen Northrop - Putnam Valley NY, US
Thomas M. Shaw - Peekskill NY, US
Richard Andre′ Wachnik - Mount Kisco NY, US
Mary Yvonne Lanzerotti Wisniewski - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50
G03F 1/00

US Classification:

716 20, 716 1, 716 3, 430 5

Abstract:

A method for analyzing circuit designs includes discretizing a design representation into pixel elements representative of a structure in the design and determining at least one property for each pixel element representing a portion of the design. Then, a response of the design is determined due to local properties across the design.

US Patent:

7470613, Dec 30, 2008

Filed:

Jan 4, 2007

Appl. No.:

11/619748

Inventors:

Birendra N. Agarwala - Hopewell Junction NY, US
Eric M. Coker - Burlington VT, US
Anthony Correale, Jr. - Raleigh NC, US
Hazara S. Rathore - Stormville NY, US
Timothy D. Sullivan - Underhill VT, US
Richard A. Wachnik - Mount Kisco NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/4763

US Classification:

438627, 257E21579, 438622

Abstract:

A method for forming an interconnect structure, the interconnect structure comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.

US Patent:

7989922, Aug 2, 2011

Filed:

Feb 8, 2008

Appl. No.:

12/028145

Inventors:

Randy W. Mann - Burlington NC, US
Jae-Eun Park - Wappingers Falls NY, US
Richard A. Wachnik - Mount Kisco NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/93

US Classification:

257599, 257312, 257532, 257595, 257E29344

Abstract:

An array of deep trenches is formed in a doped portion of the semiconductor substrate, which forms a lower electrode. A dielectric layer is formed on the sidewalls of the array of deep trenches. The array of deep trenches is filled with a doped semiconductor material to form an upper electrode comprising a top plate portion and a plurality of extension portions into the array of trenches. In a depletion mode, the bias condition across the dielectric layer depletes majority carriers within the top electrode, thus providing a low capacitance. In an accumulation mode, the bias condition attracts majority carriers toward the dielectric layer, providing a high capacitance. Thus, the trench metal-oxide-semiconductor (MOS) varactor provides a variable capacitance depending on the polarity of the bias.

US Patent:

8020138, Sep 13, 2011

Filed:

Jun 2, 2008

Appl. No.:

12/131476

Inventors:

Bruce Balch - Saranac NY, US
Nazmul Habib - South Burlington VT, US
Susan K. Lichtensteiger - Essex Junction VT, US
Daniel L. Stasiak - Austin TX, US
Richard A. Wachnik - Mount Kisco NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716136, 716133

Abstract:

A method is provided for characterizing performance of a chip having at least one voltage island and at least one performance screen ring oscillator (PSRO). An on-chip performance monitor (OCPM) is incorporated on the voltage island. Performance measurements of the voltage island are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) is compared to the performance measurements of the on-chip performance monitor (OCPM) to determine a systematic offset due to the voltage island. Performance models are adjusted using the systematic offset due to the voltage island.