Rene A Quarshie
age ~45
from Pflugerville, TX
- Also known as:
-
- Rene Armah Quarshie
- Rene L Quarshie
- Rene M Quarshie
- Renee Quarshie
- Rene Dortch
- Rene H
- Rene E
- Rene Quarshir
- Quarsh Rene Dortch
- Renee Qurahie
- Phone and address:
-
18916 Edinburgh Castle Rd, Pflugerville, TX 78660
302-981-1520
Rene Quarshie Phones & Addresses
- 18916 Edinburgh Castle Rd, Pflugerville, TX 78660 • 302-981-1520
- 151 Malcolm Forest Rd, New Castle, DE 19720 • 302-276-0705
- 1536 Lorson Loop, Round Rock, TX 78664 • 512-218-4721 • 512-992-0895
- 8025 Ranch Road 620, Austin, TX 78726 • 512-219-8977
- Lakeway, TX
- Newark, DE
Education
-
Degree:Associate degree or higher
Name / Title
Company / Classification
Phones & Addresses
Owner, Director
CHUBBY BABY WEAR, LLC
Business Services at Non-Commercial Site · Nonclassifiable Establishments
Business Services at Non-Commercial Site · Nonclassifiable Establishments
18916 Edinburgh Castle Rd, Pflugerville, TX 78660
Resumes
Physical Design Consultant At Synopsys
view sourceLocation:
1536 Lorson Loop, Round Rock, TX 78665
Industry:
Semiconductors
Work:
Synopsys
Physical Design Consultant at Synopsys
Freescale Semiconductor Jun 2001 - Apr 2011
Physical Design Engineer
University of Delaware Jan 1998 - May 2001
Research Assistant
Physical Design Consultant at Synopsys
Freescale Semiconductor Jun 2001 - Apr 2011
Physical Design Engineer
University of Delaware Jan 1998 - May 2001
Research Assistant
Education:
Keller School of Business Management 2007 - 2009
Master of Business Administration, Masters, International Business, Finance University of Delaware 1997 - 2001
Bachelors, Bachelor of Science, Computer Engineering
Master of Business Administration, Masters, International Business, Finance University of Delaware 1997 - 2001
Bachelors, Bachelor of Science, Computer Engineering
Skills:
Physical Design
Soc
Asic
Eda
Processors
Semiconductors
Vlsi
Tcl
Verilog
Ic
Microprocessors
Integrated Circuit Design
Static Timing Analysis
Debugging
Systemverilog
Hardware Architecture
Timing Closure
Perl
Functional Verification
Low Power Design
Mixed Signal
Rtl Design
Floorplanning
Soc
Asic
Eda
Processors
Semiconductors
Vlsi
Tcl
Verilog
Ic
Microprocessors
Integrated Circuit Design
Static Timing Analysis
Debugging
Systemverilog
Hardware Architecture
Timing Closure
Perl
Functional Verification
Low Power Design
Mixed Signal
Rtl Design
Floorplanning
Interests:
Biking
Basketball
Basketball
Languages:
English
Physical Design Consultant At Synopsys
view sourcePosition:
Physical Design Consultant at Synopsys
Location:
Austin, Texas Area
Industry:
Semiconductors
Work:
Synopsys since May 2011
Physical Design Consultant
Freescale Semiconductor Jun 2001 - Apr 2011
Physical Design Engineer
University of Delaware Jan 1998 - May 2001
Research Assistant
Physical Design Consultant
Freescale Semiconductor Jun 2001 - Apr 2011
Physical Design Engineer
University of Delaware Jan 1998 - May 2001
Research Assistant
Education:
Keller School of Business Management 2007 - 2009
MBA, International Business and Finance University of Delaware 1997 - 2001
BS, Computer Engineering
MBA, International Business and Finance University of Delaware 1997 - 2001
BS, Computer Engineering
Skills:
Physical Design
SoC
EDA
ASIC
TCL
VLSI
Timing Closure
Verilog
Semiconductors
IC
Static Timing Analysis
Perl
Low-power Design
Microprocessors
Processors
ASIC
Physical Design
TCL
EDA
SoC
SoC
EDA
ASIC
TCL
VLSI
Timing Closure
Verilog
Semiconductors
IC
Static Timing Analysis
Perl
Low-power Design
Microprocessors
Processors
ASIC
Physical Design
TCL
EDA
SoC
Interests:
Basketball, Biking
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