Raymond J Farbarik

US Patent:

7974052, Jul 5, 2011

Filed:

Apr 25, 2008

Appl. No.:

12/109679

Inventors:

Raymond J. Farbarik - Seattle WA, US
Jeremy Stephens - Seattle WA, US
Gerald J. Twomey - San Diego CA, US

Assignee:

Cray Inc. - Seattle WA

International Classification:

H02H 3/20
H02H 3/22

US Classification:

361 56, 361111, 361 911

Abstract:

One embodiment includes an integrated circuit including an input circuit, a first diode including a first anode and a first cathode, with the first cathode coupled to a first voltage, the first anode coupled to the input circuit at a node via a first mechanical switch, a second diode including a second anode and a second cathode, with the second cathode coupled to the node via a second mechanical switch, the second anode coupled to a ground and a resistor coupled to the input circuit between the integrated circuit and the node, wherein in a first mode of operating, the first mechanical switch and the second mechanical switch are conducting, and in a second mode of operating, the first and second mechanical switches are nonconducting.

US Patent:

20080285598, Nov 20, 2008

Filed:

May 14, 2007

Appl. No.:

11/748368

Inventors:

Raymond J. Farbarik - Seattle WA, US
Michael Steinberger - Chippewa Falls WI, US

Assignee:

Cray Inc - Seattle WA

International Classification:

H04L 7/04

US Classification:

370516, 375362

Abstract:

An apparatus comprising a first multiplexer circuit (MUX) to receive a plurality of clock phase signals at a corresponding plurality of MUX inputs and to output a first clock signal and a second clock signal that are out of phase with each other, a phase delay circuit to receive the output of the first MUX and to generate adjusted first and second clock signals that have reduced phase error with respect to detected edges of incoming data, an output MUX to receive the adjusted first and second clock signals and to output a recovered clock signal, and a control circuit coupled to output MUX select inputs. The control circuit includes logic circuitry to select the first adjusted clock signal as the recovered clock signal and to select the second adjusted clock signal as the recovered clock signal when the first adjusted clock signal nears a phase limit due to drift of the detected data edges. Other devices and methods are disclosed.

US Patent:

20120176711, Jul 12, 2012

Filed:

Jul 1, 2011

Appl. No.:

13/175387

Inventors:

Raymond J. Farbarik - Seattle WA, US
Jeremy Stephens - Seattle WA, US
Gerald J. Twomey - San Diego CA, US

Assignee:

Cray Inc. - Seattle WA

International Classification:

H02H 3/20

US Classification:

361 56

Abstract:

One embodiment includes an integrated circuit including an input circuit, a first diode including a first anode and a first cathode, with the first cathode coupled to a first voltage, the first anode coupled to the input circuit at a node via a first mechanical switch, a second diode including a second anode and a second cathode, with the second cathode coupled to the node via a second mechanical switch, the second anode coupled to a ground and a resistor coupled to the input circuit between the integrated circuit and the node, wherein in a first mode of operating, the first mechanical switch and the second mechanical switch are conducting, and in a second mode of operating, the first and second mechanical switches are nonconducting.