Ravi H Motwani

US Patent:

7733590, Jun 8, 2010

Filed:

Jun 21, 2006

Appl. No.:

11/472258

Inventors:

Ravi Motwani - Longmont CO, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11B 5/09
G11B 27/19

US Classification:

360 51, G9B 27025

Abstract:

Optimal synchronization mark/address mark construction. These marks can generally be referred to as sync marks. A novel means is presented by which sync marks can be generated for use within a variety of communication systems including HDD systems. The sync marks generated hereby have a largest possible minimum distance measurement that ensures highly accurate detection of the transition between the data portion and the preamble portion of information that is processed. Various types of distance measurement criteria can be employed, including a Euclidean distance measurement or a Hamming distance measurement, when selecting the sync mark from among a plurality of possible sync marks.

US Patent:

8091009, Jan 3, 2012

Filed:

May 22, 2006

Appl. No.:

11/438464

Inventors:

Ravi Motwani - Longmont CO, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11B 20/18

US Classification:

714769, 714780

Abstract:

Symbol by symbol MAP detection for signals corrupted by colored and/or signal dependent noise. A novel means is presented for recursive calculation of forward metrics (α), backward metrics (β), and corresponding soft information (e. g. , which can be provided as LLRs (log likelihood ratios)) within communication systems in which a trellis can be employed to perform demodulation of a received signal sequence. For signals that have been corrupted by colored and/or signal dependent noise, this means provides for the ability to perform novel soft information calculation for subsequent use in iterative decoding processing. Many types of communication channels can benefit from this novel means of detection including communication channels within hard disk drives (HDDs).

US Patent:

8473828, Jun 25, 2013

Filed:

Mar 24, 2010

Appl. No.:

12/730323

Inventors:

Ravi Motwani - Longmont CO, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03M 13/03

US Classification:

714792, 714796, 714755, 714786

Abstract:

Minimal hardware implementation of non-parity and parity trellis. More than one type of trellis can be represented using a minimal amount of hardware. In magnetic recording systems and other communication systems types, there is oftentimes a need to switch between trellises which support parity and ones which do not. Rules are presented herein which will ensure joint representation of more than one trellis while requiring minimal additional hardware when compared to representing only one trellis. To represent the non-parity trellis, emanating states, resultant states, and one or more expansion states (if needed) are all that is required. Any expansion states may also need to have its path metric and path memory corresponded to one of the resultant states to ensure proper detection according to the non-parity trellis.

US Patent:

8549380, Oct 1, 2013

Filed:

Jul 1, 2011

Appl. No.:

13/175459

Inventors:

Ravi H Motwani - Santa Clara CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 29/00
H03M 13/00
H03M 13/03

US Classification:

714763, 714718, 714751, 714769, 714794, 36518502, 36518509

Abstract:

Techniques for decoding levels in non-volatile memory. A level of a cell in a multi-bit non-volatile memory is read. A minimum of Log-Likelihood Ratio (LLR) and a modified LLR to decode the level, wherein the modified LLR is a function of a misplacement probability is used. A value corresponding the decoded level is written to a volatile memory.

US Patent:

8549382, Oct 1, 2013

Filed:

Dec 17, 2010

Appl. No.:

12/971831

Inventors:

Ravi H. Motwani - San Diego CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

714767, 714763

Abstract:

For storage drives with LDPC encoded data, read techniques are provided whereby an errantly read memory unit (e. g. , faulty LDPC codeword) may be recovered.

US Patent:

20070300138, Dec 27, 2007

Filed:

Jun 21, 2006

Appl. No.:

11/472227

Inventors:

Ravi Motwani - Longmont CO, US

Assignee:

Broadcom Corporation, a California Corporation - Irvine CA

International Classification:

H03M 13/03

US Classification:

714792

Abstract:

Minimal hardware implementation of non-parity and parity trellis. A novel means is presented by which more than one type of trellis can be represented using a minimal amount of hardware. In magnetic recording systems and other communication systems types, there is oftentimes a need to switch between trellises which support parity and ones which do not. A very efficient means is provided with rules which will ensure joint representation of more than one trellis while requiring minimal additional hardware when compared to representing only one trellis. To represent the non-parity trellis, emanating states, resultant states, and one or more expansion states (if needed) are all that is required. Any expansion states may also need to have its path metric and path memory corresponded to one of the resultant states to ensure proper detection according to the non-parity trellis.

US Patent:

20130007561, Jan 3, 2013

Filed:

Jul 1, 2011

Appl. No.:

13/175602

Inventors:

Ravi H. Motwani - Santa Clara CA, US

International Classification:

H03M 13/05
G06F 11/10

US Classification:

714758, 714800, 714E11032

Abstract:

An apparatus, system, and method for generating and decoding a longer linear block codeword using a shorter block length. The method comprises receiving data from a storage area and generating a codeword from the received data with an encoder, the codeword having a data portion and a parity portion, wherein the codeword has a first block length, and wherein the encoder applies a linear block code, the linear block code having a second block length that is shorter than the first block length.

US Patent:

20130259170, Oct 3, 2013

Filed:

Sep 28, 2011

Appl. No.:

13/991880

Inventors:

Ravi Motwani - Santa Clara CA, US

International Classification:

H04L 1/00

US Classification:

375341

Abstract:

Described herein are apparatus, system, and method for data synchronization via a maximum-likelihood decoder in a memory controller. The method comprises receiving a constrained codeword from a non-volatile memory (NVM) via a channel, the constrained codeword including an appended bit-stream; and decoding the received constrained codeword by reconstructing the appended bit-stream and invoking a synchronization procedure that applies a maximum-likelihood (ML) estimator to estimate locations of any insertion, deletion, or error in the reconstructed appended bit-stream.