Ramachandran K Muralidhar

US Patent:

6344403, Feb 5, 2002

Filed:

Jun 16, 2000

Appl. No.:

09/595735

Inventors:

Sucharita Madhukar - Austin TX
Ramachandran Muralidhar - Austin TX
David L. OMeara - Austin TX
Kristen C. Smith - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2120

US Classification:

438503, 117935, 438507, 438509

Abstract:

A semiconductor memory device with a floating gate that includes a plurality of nanoclusters ( ) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate ( ) upon which a tunnel dielectric layer ( ) is formed. A plurality of nanoclusters ( ) is then grown on the tunnel dielectric layer ( ). The growth of the nanoclusters ( ) may be accomplished using low pressure chemical vapor deposition (LPCVD) or ultra high vacuum chemical vapor deposition (UHCVD) processes. Such growth may be facilitated by formation of a nitrogen-containing layer ( ) overlying the tunnel dielectric layer ( ). After growth of the nanoclusters ( ), a control dielectric layer ( ) is formed over the nanoclusters ( ). In order to prevent oxidation of the formed nanoclusters ( ), the nanoclusters ( ) may be encapsulated using various techniques prior to formation of the control dielectric layer ( ). A gate electrode ( ) is then formed over the control dielectric ( ), and portions of the control dielectric, the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed.

US Patent:

6413819, Jul 2, 2002

Filed:

Jun 16, 2000

Appl. No.:

09/595821

Inventors:

Sufi Zafar - Austin TX
Ramachandran Muralidhar - Austin TX
Sucharita Madhukar - Austin TX
Daniel T. Pham - Austin TX
Michael A. Sadd - Austin TX
Chitra K. Subramanian - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 21336

US Classification:

438257, 438782

Abstract:

A semiconductor device that includes a floating gate made up of a plurality of pre-formed isolated storage elements ( ) and a method for making such a device is presented. The device is formed by first providing a semiconductor layer ( ) upon which a first gate insulator ( ) is formed. A plurality of pre-fabricated isolated storage elements ( ) is then deposited on the first gate insulator ( ). This deposition step may be accomplished by immersion in a colloidal solution ( ) that includes a solvent and pre-fabricated isolated storage elements ( ). Once deposited, the solvent of the solution ( ) can be removed, leaving the pre-fabricated isolated storage elements ( ) deposited on the first gate insulator ( ). After depositing the pre-fabricated isolated storage elements ( ), a second gate insulator ( ) is formed over the pre-fabricated isolated storage elements ( ). A gate electrode ( ) is then formed over the second gate insulator ( ), and portions the first and second gate insulators and the plurality of pre-fabricated isolated storage elements that do not underlie the gate electrode are selectively removed.

US Patent:

6583057, Jun 24, 2003

Filed:

Dec 14, 1998

Appl. No.:

09/211165

Inventors:

Prasad Alluri - Austin TX
Ramachandran Muralidhar - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2100

US Classification:

438653, 438687, 438688, 42725532

Abstract:

A method of forming a semiconductor device by placing a semiconductor substrate in a vacuum chamber and subjecting the semiconductor substrate ( ) to a sub-atmospheric pressure, and depositing a layer ( ) on the semiconductor substrate while maintaining the sub-atmospheric pressure. Deposition of the layer ( ) is carried out by sequentially (i) flowing a first reactant into the vacuum chamber at a first flow rate, (ii) reducing flow of the first reactant into the vacuum chamber to a second flow rate, and (iii) increasing flow of the first reactant into the vacuum chamber to a third flow rate.

US Patent:

6784103, Aug 31, 2004

Filed:

May 21, 2003

Appl. No.:

10/442500

Inventors:

Rajesh A. Rao - Austin TX
Tushar P. Merchant - Gilbert AZ
Ramachandran Muralidhar - Austin TX

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 2144

US Classification:

438680, 260263, 260264, 260197, 260201, 260962, 260594, 260257

Abstract:

Nanocrystals ( ) are formed in a semiconductor, such as for example, in a memory having a floating gate. A dielectric ( ) overlies a substrate ( ) and is placed in a chemical vapor deposition chamber ( ). A first precursor gas, such as disilane ( ), is flowed into the chemical vapor deposition chamber during a first phase to nucleate the nanocrystals ( ) on the dielectric with first predetermined processing conditions existing within the chemical vapor deposition chamber for a first time period. A second precursor gas, such as silane, is flowed into the chemical vapor deposition chamber during a second phase subsequent to the first phase to grow the nanocrystals under second predetermined processing conditions existing within the chemical vapor deposition chamber for a second time period.

US Patent:

6808986, Oct 26, 2004

Filed:

Aug 30, 2002

Appl. No.:

10/231556

Inventors:

Rajesh A. Rao - Austin TX
Ramachandran Muralidhar - Austin TX
Tushar P. Merchant - Gilbert AZ

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21336

US Classification:

438257, 438260, 438503

Abstract:

Nanocrystals ( ) are formed in a semiconductor, such as for example, in a memory having a floating gate. A dielectric ( ) overlies a substrate ( ) and is placed in a chemical vapor deposition chamber ( ). A first precursor gas, such as disilane ( ), is flowed into the chemical vapor deposition chamber during a first phase to nucleate the nanocrystals ( ) on the dielectric with first predetermined processing conditions existing within the chemical vapor deposition chamber for a first time period. A second precursor gas, such as silane, is flowed into the chemical vapor deposition chamber during a second phase subsequent to the first phase to grow the nanocrystals under second predetermined processing conditions existing within the chemical vapor deposition chamber for a second time period.

US Patent:

6831310, Dec 14, 2004

Filed:

Nov 10, 2003

Appl. No.:

10/705504

Inventors:

Leo Mathew - Austin TX
Ramachandran Muralidhar - Austin TX

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 2980

US Classification:

257270, 257315, 257316, 257328

Abstract:

A transistor ( ) is formed having three separately controllable gates ( ). The three gate regions may be electrically biased differently and the gate regions may have different conductivity properties. The dielectrics on the channel sidewall may be different than the dielectrics on the top of the channel. Electrical contacts to source, drain and the three gates is selectively made. By including charge storage layers, such as nanoclusters, adjacent the transistor channel and controlling the charge storage layers via the three gate regions, both volatile and non-volatile memory cells are realized using the same process to create a universal memory process. When implemented as a volatile cell, the height of the transistor and the characteristics of channel sidewall dielectrics control the memory retention characteristics. When implemented as a nonvolatile cell, the width of the transistor and the characteristics of the overlying channel dielectrics control the memory retention characteristics.

US Patent:

6903967, Jun 7, 2005

Filed:

May 22, 2003

Appl. No.:

10/443908

Inventors:

Leo Mathew - Austin TX, US
Robert F. Steimle - Austin TX, US
Ramachandran Muralidhar - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G11C011/34

US Classification:

365177, 36518533, 257 51, 257313

Abstract:

A memory having gate structures adjacent opposing sidewalls of a semiconductor structure including a channel region and a plurality of charge storage locations between the gate structures and the opposing sidewalls. The channel region is located between two current terminal regions, which in one example serve as the source/drain regions. A memory cell can be implemented in an array of memory cells wherein one gate structure is coupled to one word line and the other gate structure is coupled to another word line. In one example, each cell includes four charge storage locations, each for storing one bit of data.

US Patent:

6958265, Oct 25, 2005

Filed:

Sep 16, 2003

Appl. No.:

10/663621

Inventors:

Robert F. Steimle - Austin TX, US
Ramachandran Muralidhar - Austin TX, US
Wayne M. Paulson - Chandler AZ, US
Rajesh A. Rao - Austin TX, US
Erwin J. Prinz - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L021/8238

US Classification:

438211, 438257

Abstract:

A process of forming a device with nanoclusters. The process includes forming nanoclusters (e. g. silicon nanocrystals) and forming an oxidation barrier layer over the nanoclusters to inhibit oxidizing agents from oxidizing the nanoclusters during a subsequent formation of a dielectric of the device. At least a portion of the oxidation barrier layer is removed after the formation of the dielectric. In one example, the device is a memory wherein the nanoclusters are utilized as charge storage locations for charge storage transistors of the memory. In this example, the oxidation barrier layer protects the nanoclusters from oxidizing agents due to the formation of gate dielectric for high voltage transistors of the memory.