Search

Rajasekhar R Allu

from Dallas, TX

Also known as:
  • Rajasekhar Reddy Allu

Rajasekhar Allu Phones & Addresses

  • Dallas, TX

Us Patents

  • Noise Estimation Using User-Configurable Information

    view source
  • US Patent:
    20220263979, Aug 18, 2022
  • Filed:
    May 9, 2022
  • Appl. No.:
    17/739291
  • Inventors:
    - Dallas TX, US
    Mihir Narendra MODY - Bangalore, IN
    Rajasekhar Reddy ALLU - Plano TX, US
    Niraj NANDAN - Plano TX, US
    Shashank DABRAL - Allen TX, US
  • International Classification:
    H04N 5/217
    H04N 9/04
    H04N 5/357
  • Abstract:
    In some examples, a method comprises receiving pixel data from an image capture device having a color filter, wherein the pixel data represents a portion of an image. The method further includes performing wavelet decomposition on the pixel data to produce decomposed pixel data and determining a local intensity of the pixel data. The method also includes determining a noise threshold value based on the local intensity and a noise intensity function that is based on the color filter; determining a noise value for the pixel data based on the decomposed pixel data and the noise threshold value; and correcting the pixel data based on the noise value to produce an output image.
  • Efficient And Flexible Color Processor

    view source
  • US Patent:
    20230086775, Mar 23, 2023
  • Filed:
    Dec 1, 2022
  • Appl. No.:
    18/072813
  • Inventors:
    - Dallas TX, US
    Shashank DABRAL - Allen TX, US
    Rajasekhar ALLU - Plano TX, US
    Niraj NANDAN - Plano TX, US
  • International Classification:
    H04N 9/04
    G06T 1/20
    H04N 9/67
  • Abstract:
    An image signal processor includes a first matrix processing circuit, a post processing circuit, a second matrix processing circuit, and a split visual and analytics circuit. The first matrix processing circuit is configured to receive a plurality of component images generated based on an image captured by an image sensor and generate a plurality of first matrix outputs based on the plurality of component images. The post processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a first luminance component of the image and a chrominance component of the image. The second matrix processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a second luminance component of the image and a saturation component of the image. The split visual and analytics circuit is configured to generate visual and analytic data of the image.
  • Local Memory Use For Perspective Transform Engine

    view source
  • US Patent:
    20210326050, Oct 21, 2021
  • Filed:
    Apr 16, 2021
  • Appl. No.:
    17/233361
  • Inventors:
    - Dallas TX, US
    Niraj NANDAN - Plano TX, US
    Rajasekhar Reddy ALLU - Plano TX, US
  • International Classification:
    G06F 3/06
    G06F 13/28
  • Abstract:
    An integrated circuit includes: a local memory; and a first processing circuit coupled to the local memory. The first processing component is configured to: receive a first set of image data; perform a first image processing operation on the first set of image data to produce a second set of image data; and store at least some of the second set of image data into the local memory. The integrated circuit also includes a second processing circuit coupled to the local memory and configured to: receive at least some of the second set of image data from the local memory; and perform a second image processing operation on the second set of image data to produce a third set of image data.
  • Systems, Methods, And Apparatus To Enable Data Aggregation And Adaptation In Hardware Acceleration Subsystems

    view source
  • US Patent:
    20210209041, Jul 8, 2021
  • Filed:
    Dec 31, 2020
  • Appl. No.:
    17/139970
  • Inventors:
    - Dallas TX, US
    Rajasekhar Reddy Allu - Plano TX, US
    Brian Chae - Duluth GA, US
    Mihir Mody - Bangalore, IN
  • International Classification:
    G06F 13/28
    G06F 9/48
    G06F 13/40
    G06F 13/16
  • Abstract:
    Methods, apparatus, systems, and articles of manufacture are disclosed herein to enable data aggregation and pattern adaptation in hardware acceleration subsystems. In some examples, a hardware acceleration subsystem includes a first scheduler, a first hardware accelerator coupled to the first scheduler to process at least a first data element and a second data element, and a first load store engine coupled to the first hardware accelerator, the first load store engine configured to communicate with the first scheduler at a superblock level by sending a done signal to the first scheduler in response to determining that a block count is equal to a first BPR value and aggregate the first data element and the second data element based on the first BPR value to generate a first aggregated data element.
  • Low Latency Streaming Remapping Engine

    view source
  • US Patent:
    20210209722, Jul 8, 2021
  • Filed:
    Jun 23, 2020
  • Appl. No.:
    16/909710
  • Inventors:
    - Dallas TX, US
    Rajasekhar Reddy ALLU - Plano TX, US
    Mihir Narendra MODY - Bengaluru, IN
  • International Classification:
    G06T 1/60
    G06F 9/50
    G06F 9/54
  • Abstract:
    A lens distortion correction function operates by backmapping output images to the uncorrected, distorted input images. As a vision image processor completes processing on the image data lines needed for the lens distortion correction function to operate on a group of output, undistorted image lines, the lens distortion correction function begins processing the image data. This improves image processing pipeline delays by overlapping the operations. The vision image processor provides output image data to a circular buffer in SRAM, rather than providing it to DRAM. The lens distortion correction function operates from the image data in the circular buffer. By operating from the SRAM circular buffer, access to the DRAM for the highly fragmented backmapping image data read operations is removed, improving available DRAM bandwidth. By using a circular buffer, less space is needed in the SRAM. The improved memory operations further improve the image processing pipeline delays.
  • Error Handling In A Geometric Correction Engine

    view source
  • US Patent:
    20210209737, Jul 8, 2021
  • Filed:
    Dec 11, 2020
  • Appl. No.:
    17/119714
  • Inventors:
    - Dallas TX, US
    Rajasekhar Reddy Allu - Plano TX, US
    Niraj Nandan - Plano TX, US
    Mihir Narendra Mody - Bangalore, IN
  • International Classification:
    G06T 5/00
    G06T 7/60
    G06T 3/00
    G06T 11/40
  • Abstract:
    A method for error handling in a geometric correction engine (GCE) is provided that includes receiving configuration parameters by the GCE, generating, by the GCE in accordance with the configuration parameters, output blocks of an output frame based on corresponding blocks of an input frame, detecting, by the GCE, a run-time error during the generating, and reporting, by the GCE, an event corresponding to the run-time error.
  • Noise Estimation Using User-Configurable Information

    view source
  • US Patent:
    20200396356, Dec 17, 2020
  • Filed:
    Jun 14, 2019
  • Appl. No.:
    16/442137
  • Inventors:
    - Dallas TX, US
    Mihir Narendra MODY - Bangalore, IN
    Rajasekhar Reddy ALLU - Plano TX, US
    Niraj NANDAN - Plano TX, US
    Shashank DABRAL - Allen TX, US
  • International Classification:
    H04N 5/217
    H04N 5/357
    H04N 9/04
  • Abstract:
    In some examples, a method comprises receiving pixel data from an image capture device having a color filter, wherein the pixel data represents a portion of an image. The method further includes performing wavelet decomposition on the pixel data to produce decomposed pixel data and determining a local intensity of the pixel data. The method also includes determining a noise threshold value based on the local intensity and a noise intensity function that is based on the color filter; determining a noise value for the pixel data based on the decomposed pixel data and the noise threshold value; and correcting the pixel data based on the noise value to produce an output image.
  • Image Data Processing For Multi-Exposure Wide Dynamic Range Image Data

    view source
  • US Patent:
    20200389581, Dec 10, 2020
  • Filed:
    Aug 24, 2020
  • Appl. No.:
    17/001398
  • Inventors:
    - Dallas TX, US
    Rajasekhar Reddy Allu - Plano TX, US
  • International Classification:
    H04N 5/235
    H04N 5/217
    H04N 5/265
    H04N 9/73
  • Abstract:
    Disclosed examples include integrated circuits, merge circuits and methods of processing multiple-exposure image data, in which a single pre-processing circuit is used for pre-processing first input exposure data associated with a first exposure of the image, and then for pre-processing second input exposure data associated with a second exposure of the image, and the first and second pre-processed exposure data are merged to generate merged image data for tone mapping and other post-processing. An example merge circuit includes a configurable gain circuit to apply a gain to the first and/or second exposure data, as well as a configurable weighting circuit with a weight calculation circuit and a motion adaptive filter circuit to compute a first and second weight values for merging the pre-processed first and second exposure data.

Resumes

Rajasekhar Allu Photo 1

Senior Lead Engineer

view source
Location:
Dallas, TX
Industry:
Semiconductors
Work:
Texas Instruments
Senior Lead Engineer

Texas Instruments
Lead Engineer

Texas Instruments Jun 2006 - Jun 2008
Senior Design Engineer

Texas Instrumnets India Apr 2004 - May 2006
Hw Engineer

Qualcore Logic Jan 2002 - Mar 2004
Senior Design Engineer
Education:
Jawaharlal Nehru Technological University 1997 - 2001
Bachelors, Bachelor of Technology, Electronics, Engineering, Communications
Aprs School 1992 - 1995
Skills:
Asic
Verilog
Timing Closure
Rtl Design
Soc
Functional Verification
Low Power Design
Vhdl
Arm
Image Processing
Syntheyes
Omap
Multimedia
Fpga
Multicultural
Rajasekhar Allu Photo 2

Programmer Analyst At Fedex Services

view source
Position:
Programmer Analyst at FedEx Services
Location:
Memphis, Tennessee
Industry:
Computer Software
Work:
FedEx Services - Greater Memphis Area since Feb 2011
Programmer Analyst
Education:
SJSU 2008 - 2010
MS, Computer Engineering

Googleplus

Rajasekhar Allu Photo 3

Rajasekhar Allu

Rajasekhar Allu Photo 4

Rajasekhar Allu


Get Report for Rajasekhar R Allu from Dallas, TX
Control profile