A method for eliminating races commences with the testing of an integrated circuit for races. If a clock signal which is produced by the integrated circuit is deemed to be a cause of races, at least one transistor region is clipped from an output driver of a clock gater which produces the clock signal. The clipping is performed by reconstructing at least one mask which is used to define the output driver during fabrication of the integrated circuit. In a similar fashion, a method for increasing the rise/fall time of clock edges in an integrated circuit commences with the identification of a clock signal with a clock edge having a poor rise/fall time. The rise/fall time of such a clock edge is increased by clipping at least one transistor region from an output driver of a clock gater which produces the clock signal. Once again, the clipping is performed by reconstructing at least one mask which is used to define the output driver during fabrication of the integrated circuit.
System And Method For Transferring Data From A Lower Frequency Clock Domain To A Higher Frequency Clock Domain
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F001/06
US Classification:
713501, 713500, 713503, 375354, 375355
Abstract:
A system and method for transferring data from circuitry disposed in a lower frequency clock domain actuated by a first clock signal to circuitry disposed in a higher frequency clock domain actuated by a second clock signal, wherein the first and second clock signals are provided in a predetermined frequency ratio. A latch gated by the first clock signal is operable to generate latched data, which is provided to a first register disposed in the higher frequency clock domain. The first register, clocked by a modified clock signal that is synthesized by a logic circuit using the second clock signal and a plurality of intermediary clock signals derived from the second clock signal, is operable to generate registered data. A second register is operable to synchronize the registered data into a data output for subsequent use by the circuitry disposed in the higher clock frequency domain.
System And Method For Transferring Data From A Higher Frequency Clock Domain To A Lower Frequency Clock Domain
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F001/06
US Classification:
713501, 713500, 713503, 375354, 375355
Abstract:
A system and method for transferring data from circuitry disposed in a higher frequency clock domain actuated by a first clock signal to circuitry disposed in a lower frequency clock domain actuated by a second clock signal, wherein the first and second clock signals are provided in a predetermined frequency ratio. A first latch gated by a first modified clock signal that is derived from the first clock signal and plurality of intermediary signals relating thereto is operable to generate a first latched data output, which is provided to a second latch disposed in the lower frequency clock domain. The second latch gated by a second modified clock signal that is synthesized using the second clock signal and at least one intermediary clock signal derived therefrom is operable to generate a second latched output. A register is operable to synchronize the second latched data output into a synchronized data output for subsequent use by the circuitry disposed in the lower clock frequency domain.
Double-High Dimm With Dual Registers And Related Methods
Brian M. Johnson - Allen TX, US John Nerl - Londonderry NH, US Michael C. Day - Allen TX, US Vicki L. Smith - NW Province, CM Richard A. Schumacher - Dallas TX, US Rajakrishnan Radjassamy - Plano TX, US June E. Goodwin - Plano TX, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G11C 5/06
US Classification:
365 63, 36523008, 361764, 716 15
Abstract:
One memory module includes a printed circuit board comprising an upper row of memory integrated circuits, a lower row of memory integrated circuits, and a first addressing register and a second addressing register, the first addressing register and a second addressing register each having at least one of address and control input routing primarily provided in a first layer, the first addressing register coupled to the upper row of memory integrated circuits and the second addressing register coupled to the lower row of memory integrated circuits.
Reset Scheme For I/O Pads In A Source Synchronous System
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
H04B 1/38
US Classification:
375220
Abstract:
A system and method for providing reset control between two integrated circuit domains (ICDs) disposed in a synchronous relationship. Upon reset, control signals are generated in a first ICD for resetting driver/receiver circuitry therein in a phased manner. An inter-ICD reset control signal is generated by the first ICD for transmission to the second ICD, wherein the inter-ICD reset control signal is operable to reset the second ICD's driver/receiver circuitry and other components therein.
System And Method For Establishing A Known Timing Relationship Between Two Clock Signals
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
H04L 7/00 H04L 5/16
US Classification:
375354, 713400, 375219, 375355
Abstract:
A system and method for establishing a known timing relationship between two clock signals, wherein a first clock signal is operable to clock data transfer operations from a transmitter domain to a receiver domain and a second clock signal is operable to be transported to the receiver domain. Circuitry is provided for detecting an edge in a global framework clock (GFC) signal that is supplied to the transmitter domain. A common alignment signal is manufactured that is based at least in part upon the GFC signal. A multiplexer and register arrangement is operable to output the second clock signal in response to the common alignment signal which is also used for gating the data transfer operations clocked by the first clock signal.
Register-Based De-Skew System And Method For A Source Synchronous Receiver
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 1/12
US Classification:
713503, 713500
Abstract:
A register-based de-skew system and method for a source synchronous receiver circuit domain. In one embodiment, a de-skew strobe generator operates responsive to at least one incoming strobe signal in order to generate a plurality of one-hot de-skew strobe signals. A plurality of de-skew registers receive the same input data pulses from a transmitter circuit domain. By clocking the de-skew registers with the one-hot de-skew strobe signals, the input data pulses are stretched into spread data pulses having an extended timing window. A plurality of multiplexers multiplex the spread data pulses, whereupon the multiplexed data is registered using a clock signal associated with the receiver circuit domain.
System And Method For Estimating Power Consumption For At Least A Portion Of An Integrated Circuit
A system and method for estimating power consumption of at least a portion of an integrated circuit (IC). The IC is segmented into a hierarchical sub-block level structure such that within each sub-block and between sub-blocks of the same level, power consumption components are identified so that the power consumption for each sub-block may be estimated based on an application of probabilistic activity profiles associated with the power consumption components.