Paul M Wayner

US Patent:

7664212, Feb 16, 2010

Filed:

Oct 19, 2005

Appl. No.:

11/252723

Inventors:

Paul M. Wayner - Fairfax VA, US
Adrian R. Macias - Vista CA, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H04B 1/10

US Classification:

375349, 375354, 713322

Abstract:

A apparatus () and method () are presented for preventing glitches and data loss in an Digital Base Band (DBB) portion () of an Ultra Wideband (UWB) receiver. a first and a second recovered clock () and an external clock () can be input to a switch (). Logical rules () can be used to determine conditions under which to hold the state of an output clock () based on the states of a first clock () and a second clock () and the state of a switch request signal (). In addition to holding the state of the output clock, a first data stream () associated with the first clock and a second data stream () associated with the second clock can be synchronized such that when switching from the first to the second clock no data loss will be experienced in the data stream.

US Patent:

20040067765, Apr 8, 2004

Filed:

Oct 8, 2003

Appl. No.:

10/680491

Inventors:

Paul Wayner - Centreville VA, US

International Classification:

H04B007/005

US Classification:

455/502000

Abstract:

A received wireless signal contains a plurality of path components, each having a phase indeterminate data stream derived from an original data stream. The receiver splits the received signal into N signal copies for N raking channels, which correlate each of the N signal copies with N locally generated signals, respectively, to generate N correlated signals. Each of the N correlated signals carries an estimated phase indeterminate data stream. The raking channels then synchronize each of the correlated signals to a system clock in phase and frequency to generate N synchronized signals. The N raking channels then align the N synchronized signals to generate N aligned signals, each of which carries an aligned path data stream that is normalized in time with respect to the other aligned signals. Finally the receiver combines the aligned signals to produce an estimated original data stream.

US Patent:

20070079024, Apr 5, 2007

Filed:

Sep 30, 2005

Appl. No.:

11/239040

Inventors:

Paul Wayner - Fairfax VA, US

International Classification:

G06F 5/00

US Classification:

710052000

Abstract:

A circuit () and method () are presented for detecting non-volatile memory (NVM) devices () associated with computing device during a processor boot sequence. The NVM devices have corresponding starting addresses ()and the processor begins operation from a first starting address associated with a first NVM devices after a reset interval. The circuit includes NVM device detectors which determine whether the NVM devices are present by reading () an authentication code including an identifier, a codeword, a NVM size, or a NVM type from a predetermined location within the each of the NVM devices if present. If the NVM device is not present, the detector returns an instruction () for the processor to continue execution at a starting addresses for a next NVM device.