Paul John Patchen

US Patent:

7210051, Apr 24, 2007

Filed:

Nov 7, 2003

Appl. No.:

10/703279

Inventors:

Paul J. Patchen - Arlington TX, US
William V. Miller - Arlington TX, US

Assignee:

VIA Technologies, Inc. of Taiwan - Taipei

International Classification:

G06F 1/04

US Classification:

713500, 713228, 714 15

Abstract:

An improved program status register is disclosed with a feature to handle state change for a processor and its memory subsystem. The program status register comprises a clock, at least one update value for updating the program status register to a second value from a first value when an update enable signal is received, a sampled program status register storing the first value of the program status register, and a state change sampling register generating a synchronized state change signal from a state change indication signal and the clock. When the update enable signal is initially received and a state change indication signal is further received thereafter during a first clock cycle, an updated output of the program status register is restored through a first selection module triggered by the synchronized state change signal to the first value in a second clock cycle following the first clock cycle.

US Patent:

7594103, Sep 22, 2009

Filed:

Nov 15, 2002

Appl. No.:

10/294578

Inventors:

Paul J. Patchen - Arlington TX, US
William V. Miller - Arlington TX, US

Assignee:

VIA-Cyrix, Inc. - Fremont CA

International Classification:

G06F 9/30

US Classification:

712244

Abstract:

A pipeline processing microprocessor includes a storage unit for storing instructions and a fetch unit for requesting and fetching an instruction from the instructions in the storage unit. Upon an interrupt condition, the fetch unit eliminates from a request queue a previously requested instruction that precedes the interrupt condition.

US Patent:

49704079, Nov 13, 1990

Filed:

Jul 12, 1989

Appl. No.:

7/379684

Inventors:

Paul J. Patchen - Arlington TX

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03K 3289
H03K 326
H03K 329

US Classification:

3072722

Abstract:

A conventional D-type flip-flop transfers the data input D to a first output Q and a second output Q', where the second output Q' is the complement of the first output Q, on the transitions of a clock signal CK. This involves the transfer of data from a master latch and a series-connected slave latch which are loaded on alternating phases of the clock signal CK. The present invention provides for asynchronous loading of replacement data into the flip-flop by using a tri-stable buffer in both the master and slave latches. In response to a load signal LD, replacement data is injected into the master and slave latches overriding the current value stored at the Q and Q' outputs. This occurs because the load signal disables the normally active buffers while activating the loading buffers causing the normally active data path to go the tri-state condition. The state of the clock signal CK is of no importance to the outcome of the asynchronous load operation since both the master and the slave latch are overwritten during the load phase.

US Patent:

57489815, May 5, 1998

Filed:

Nov 13, 1996

Appl. No.:

8/748970

Inventors:

Paul J. Patchen - Arlington TX
Hon C. Fung - Arlington TX
Fred Leung - Cupertino CA
Steven McGinness - San Jose CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 900

US Classification:

395828

Abstract:

An architecture is described for a single chip microcontroller wherein the microcode stored in the microcontroller's program memory may be easily modified without refabrication or removal of the microcontroller from its target environment. This is made possible by the utilization of a RAM based architecture for program memory instead of the traditional ROM based architecture.

US Patent:

49655248, Oct 23, 1990

Filed:

Aug 11, 1989

Appl. No.:

7/393011

Inventors:

Paul J. Patchen - Arlington TX

Assignee:

National Semiconductor Corp. - Santa Clara CA

International Classification:

H03K 1700
H03K 513
H03K 117
H03K 1756

US Classification:

328 72

Abstract:

Clock select circuitry is provided which allows CPU operation at the crystal frequency or one-half the crystal frequency. Frequency selection is accomplished under CPU control and circuitry is added to insure that the a glitch free clock change can be performed on the fly. The glitch free clock select insures that no half T state is less than what a full speed half T state would be. By gating the appropriate phases of the half speed clock and the full speed clock to control the clocking of a flip flop, the point at which the clock selection multiplexer is switched can be controlled. In speeding up the clock, the speed change occurs on the falling edge of the full speed clock provided that the half speed clock is low. When slowing down the clock, the speed change occurs on the rising edge of the half speed clock.

US Patent:

48517160, Jul 25, 1989

Filed:

Jun 9, 1988

Appl. No.:

7/204637

Inventors:

William M. Needles - Arlington TX
Paul J. Patchen - Arlington TX

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03K 19017
H03K 19094

US Classification:

307463

Abstract:

A single plane dynamic decoder wherein a typical decoder row comprises a P-channel transistor connected between a positive supply and a first node, a second N-channel transistor connected between ground potential and a second node, and a plurality of series-connected devices connected between the first node and the second node. The gates of the intermediate N-channel devices are connected to a corresponding input signal such that the intermediate devices are enabled or disabled depending on the state of the associated input. The gate of the P-channel device is connected to a clock signal such that it is enabled by a first clock phase and disabled by a second clock phase. The N-channel device is connected to the clock signal such that it is enabled by the second clock phase and disabled by the first clock phase. Thus, the first node is precharged when the P-channel device is enabled. This precharge activity occurs serially and hierarchically down the row depending on the state of the respective input signals.

US Patent:

48624829, Aug 29, 1989

Filed:

Jun 16, 1988

Appl. No.:

7/207772

Inventors:

Paul J. Patchen - Arlington TX

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03M 512

US Classification:

375 87

Abstract:

A receiver for extracting binary data from a Manchester-encoded input signal. Sampling logic samples the input signal at a frequency greater than the bit cell rate to detect input edges. The sampling logic output is divided to provide a sampling clock having a frequency greater than the bit cell rate and which is synchronized with the input signal. The sampling clock is then utilized to sample the first bit cell half of the sampled input signal. The value obtained by sampling the first bit cell half is then inverted to provide extracted binary data.