Paul S Durley

US Patent:

8416905, Apr 9, 2013

Filed:

Sep 24, 2010

Appl. No.:

12/889893

Inventors:

Huimin Chen - Portland OR, US
Chunyu Zhang - Folsom CA, US
Paul S. Durley - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 7/02

US Classification:

375360

Abstract:

Systems and methods of operating a serial interconnect interface provide for generating a pulse in response to a state change in a data signal of the serial interface interconnect, and transmitting the pulse from a physical layer of the serial interconnect interface to a link layer of the serial interconnect interface. The duration of the pulse can be selected based on whether the state change corresponds to an end of packet (EOP) condition. In addition, the data signal may include a non return to zero invert (NRZI) encoded signal, wherein the pulse is part of a digital NRZI signal.

US Patent:

8612782, Dec 17, 2013

Filed:

Mar 31, 2011

Appl. No.:

13/076800

Inventors:

Reed D. Vilhauer - Portland OR, US
Darren S. Crews - Portland OR, US
Paul S. Durley - Portland OR, US
Kevin R. Mullen - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/00

US Classification:

713300

Abstract:

A power control manager includes a processor to compute available power from a power source and a comparator to compare the available power to an amount of power to concurrently operate a plurality of sub-systems of an electronic device at full or a predetermined power. The processor generates one or more control signals in response to a decision signal output from the comparator. The control signals may indicate that a maximum power setting is to be set for a first sub-system and a reduced non-zero power setting is to be set for a second sub-system of the plurality of sub-systems. The sub-systems may be different sub-systems of a smartphone or another electronic device.

US Patent:

8638072, Jan 28, 2014

Filed:

Apr 1, 2011

Appl. No.:

13/078216

Inventors:

Reed D. Vilhauer - Portland OR, US
Paul S. Durley - Portland OR, US
Darren S. Crews - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H02J 7/04
H02J 7/16

US Classification:

320162

Abstract:

An apparatus may comprise first circuitry arranged to draw current from a charging source at multiple current levels and second circuitry arranged to determine a charging current capacity of the charging source using the first circuitry.

US Patent:

20030070104, Apr 10, 2003

Filed:

Jul 30, 2001

Appl. No.:

09/918130

Inventors:

Robert Bruckner - Wilsonville OR, US
Paul Durley - Portland OR, US
William Sanderson - Hillsboro OR, US

International Classification:

G06F001/26

US Classification:

713/320000

Abstract:

A technique includes receiving an indication of a thermal event in a processor. The processor is part of a computer system. In response to the indication, the processor is powered down, and subsequent to the powering down of the processor, other components of the computer are powered down.

US Patent:

20130235913, Sep 12, 2013

Filed:

Apr 4, 2013

Appl. No.:

13/856484

Inventors:

Huimin Chen - Portland OR, US
Chunyu Zhang - Folsom CA, US
Paul S. Durley - Portland OR, US

International Classification:

H04L 7/033

US Classification:

375219, 375295

Abstract:

Systems and methods of operating a serial interconnect interface provide for generating a pulse in response to a state change in a data signal of the serial interface interconnect, and transmitting the pulse from a physical layer of the serial interconnect interface to a link layer of the serial interconnect interface. The duration of the pulse can be selected based on whether the state change corresponds to an end of packet (EOP) condition. In addition, the data signal may include a non return to zero invert (NRZI) encoded signal, wherein the pulse is part of a digital NRZI signal.

US Patent:

20180224923, Aug 9, 2018

Filed:

Feb 8, 2017

Appl. No.:

15/427682

Inventors:

- Santa Clara CA, US
Senaka Cuda Bandara Ratnayake - El Dorado Hills CA, US
Paul S. Durley - Portland OR, US
Moorthy Rajesh - Folsom CA, US
Darren S. Crews - Hillsboro OR, US

International Classification:

G06F 1/32
G10L 15/28
G10L 15/08

Abstract:

Systems and techniques for lower power key phrase detection are disclosed herein. An audio sample may be captured in a power management integrated circuit (PMIC). Here, the PMIC is physically different than a sensor circuit of an integrated system and the PMIC has a lower power leakage than the sensor circuit. The integrated system may be awoken upon a trigger. The audio sample may then be transferred to the integrated system to perform key phrase detection (KPD). The integrated system may be put to sleep in response to completion of the KPD.

US Patent:

20150333735, Nov 19, 2015

Filed:

May 15, 2014

Appl. No.:

14/278566

Inventors:

VINU K. ELIAS - Austin TX, US
SRIDHARAN RANGANATHAN - San Ramon CA, US
PAUL S. DURLEY - Portland OR, US

International Classification:

H03K 3/01

Abstract:

Disclosed herein is a system to minimize power leakage. The system is configured to include a system-on-chip (SOC). The SOC is configured to include a Universal Serial Bus (USB) physical subsystem and system firmware, wherein the system firmware conveys USB related events to the SOC. The system is configured to include a power management apparatus, where the power management apparatus includes USB wake functionality and USB On-the-Go (OTG) functionality.