Nisha Ananthakrishnan from 2443 Locust Ct, Chandler, AZ 85286, age 47, Phone: 480-699-9514

Us Patents

Magnetic Particles For Low Temperature Cure Of Underfill
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US Patent:

20090170247, Jul 2, 2009
Filed:

Dec 28, 2007
Appl. No.:

11/966933
Inventors:

Linda A. SHEKHAWAT - Tucson AZ, US
Gregory S. CONSTABLE - Chandler AZ, US
Youzhi E. XU - Gilbert AZ, US
Nisha ANANTHAKRISHNAN - Chandler AZ, US
International Classification:

H01L 21/50
US Classification:

438127, 257E21499
Abstract:

Electronic devices and methods for fabricating electronic devices are described. One embodiment includes a method comprising providing a first body and a second body, and electrically coupling the first body to the second body using a plurality of solder bumps, wherein a gap remains between the first body and the second body. The method also includes placing an underfill material into the gap between the first body and the second body, the underfill material comprising magnetic particles in a polymer composition. The method also includes curing the underfill material in the gap by applying a magnetic field powered by alternating current, to induce heat in the magnetic particles, wherein the heat in the magnetic particles heats the polymer composition, and the magnetic field is applied for a sufficient time to cure the polymer composition. Other embodiments are described and claimed.

Microelectronic Package With Wear Resistant Coating
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US Patent:

20100078806, Apr 1, 2010
Filed:

Sep 30, 2008
Appl. No.:

12/242398
Inventors:

Nirupama Chakrapani - Gilbert AZ, US
Vijay S. Wakharkar - Paradise Valley AZ, US
Janet Feng - Chandler AZ, US
Nisha Ananthakrishnan - Chandler AZ, US
Gregory S. Constable - Chandler AZ, US
International Classification:

H01L 23/34
H01L 21/00
US Classification:

257712, 438106, 257E23101, 257E21001
Abstract:

A microelectronic package is provided. The microelectronic package includes a semiconductor substrate and a die having a top surface and a bottom surface, wherein the bottom surface of the die is coupled to the semiconductor substrate. The microelectronic package also includes a nanomaterial layer disposed on the top surface of the die.

Flexible Underfill Compositions For Enhanced Reliability
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US Patent:

20120074597, Mar 29, 2012
Filed:

Sep 24, 2010
Appl. No.:

12/890545
Inventors:

Dingying Xu - Maricopa AZ, US
Nisha Ananthakrishnan - Chandler AZ, US
Hong Dong - Perry Hall MD, US
Rahul N. Manepalli - Chandler AZ, US
Nachiket Raravikar - Gilbert AZ, US
Gregory S. Constable - Chandler AZ, US
International Classification:

H01L 23/48
C09D 7/12
US Classification:

257783, 10628714, 257E2301
Abstract:

Underfill materials for fabricating electronic devices are described. One embodiment includes an underfill composition including an epoxy mixture, an amine hardener component, and a filler. The epoxy mixture may include a first epoxy comprising a bisphenol epoxy, a second epoxy comprising a multifunctional epoxy, and a third epoxy comprising an aliphatic epoxy, the aliphatic epoxy comprising a silicone epoxy. The first, second, and third epoxies each have a different chemical structure. Other embodiments are described and claimed.

Fluxing-Encapsulant Material For Microelectronic Packages Assembled Via Thermal Compression Bonding Process
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US Patent:

20130263446, Oct 10, 2013
Filed:

Sep 30, 2011
Appl. No.:

13/994674
Inventors:

Sivakumar Nagarajan - Chandler AZ, US
Sandeep Razdan - Chandler AZ, US
Nisha Ananthakrishnan - Chandler AZ, US
Craig J. Weinman - Mesa AZ, US
Kabirkumar J. Mirpuri - Scottsdale AZ, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H05K 3/34
H01L 21/56
US Classification:

29840, 29841
Abstract:

A fluxing-encapsulant material and method of use thereof in a thermal compression bonding (TCB) process is described. In an embodiment, the TCB process includes ramping the bond head to 250 C.-300 C. at a ramp rate of 50 C./second-100 C./second. In an embodiment, the fluxing-encapsulant material comprising one or more epoxy resins having an epoxy equivalent weight (EEW) of 150-1,000, a curing agent, and a fluxing agent having a mono-carboxylic acid or di-carboxylic acid and a pKa of 4-5.

Techniques And Configurations For Surface Treatment Of An Integrated Circuit Substrate
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US Patent:

20140061902, Mar 6, 2014
Filed:

Aug 31, 2012
Appl. No.:

13/601788
Inventors:

Suriyakala Ramalingam - Chandler AZ, US
Rajen S. Sidhu - Chandler AZ, US
Nisha Ananthakrishnan - Chandler AZ, US
Sivakumar Nagarajan - Chandler AZ, US
Wei Tan - Chandler AZ, US
Sandeep Razdan - Chandler AZ, US
Vipul V. Mehta - Chandler AZ, US
International Classification:

H01L 23/498
H01L 21/28
H01L 21/50
H01L 23/48
US Classification:

257738, 257741, 438612, 438107, 257777, 257E2301, 257E23069, 257E21158, 257E21499
Abstract:

Embodiments of the present disclosure are directed towards techniques and configurations for surface treatment of an integrated circuit (IC) substrate. In one embodiment, an apparatus includes an integrated circuit substrate, an interconnect structure disposed on the integrated circuit substrate, the interconnect structure being configured to route electrical signals to or from the integrated circuit substrate and comprising a metal surface, and a protective layer disposed on the metal surface of the interconnect structure, the protective layer comprising a first functional group bonded with the metal surface and a second functional group bonded with the first functional group, wherein the second functional group is hydrophobic to inhibit contamination of the metal surface by hydrophilic materials and further inhibits oxidation of the metal surface. Other embodiments may be described and/or claimed.

Underfill Material For Integrated Circuit (Ic) Package
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US Patent:

20210242102, Aug 5, 2021
Filed:

Feb 4, 2020
Appl. No.:

16/781894
Inventors:

- Santa Clara CA, US
Ziyin LIN - Chandler AZ, US
Nisha ANANTHAKRISHNAN - Chandler AZ, US
International Classification:

H01L 23/31
H05K 1/18
C08L 63/00
C08L 75/04
C08L 67/00
C08L 83/04
C08K 5/3432
C08K 3/36
C08K 3/22
C08K 3/38
H01L 23/50
Abstract:

Embodiments herein describe techniques for an IC package including an electronic component, and an underfill material around or below the electronic component to support the electronic component. The underfill material includes a resin and a thermolatent onium salt as a cationic cure for the underfill material. The thermolatent onium salt comprises an organic cation with a heteroatom center, and an anion including metalloid fluoride. The heteroatom center includes an iodonium, sulphonium, phosphonium, or N-containing onium. Other embodiments may be described and/or claimed.

Microelectronics Package Comprising A Package-On-Package (Pop) Architecture With Inkjet Barrier Material For Controlling Bondline Thickness And Pop Adhesive Keep Out Zone
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US Patent:

20210066155, Mar 4, 2021
Filed:

Aug 30, 2019
Appl. No.:

16/557784
Inventors:

- Santa Clara CA, US
Shripad GOKHALE - Gilbert AZ, US
Nick ROSS - Chandler AZ, US
Amram EITAN - Scottsdale AZ, US
Nisha ANANTHAKRISHNAN - Chandler AZ, US
Robert M. NICKERSON - Chandler AZ, US
Purushotham Kaushik MUTHUR SRINATH - Chandler AZ, US
Yang GUO - Chandler AZ, US
John C. DECKER - Tempe AZ, US
Hsin-Yu LI - Chandler AZ, US
International Classification:

H01L 23/373
H01L 21/56
H01L 21/768
H01L 21/02
H01L 23/48
Abstract:

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

Wafer Level Passive Heat Spreader Interposer To Enable Improved Thermal Solution For Stacked Dies In Multi-Chips Package And Warpage Control
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US Patent:

20210057381, Feb 25, 2021
Filed:

Aug 22, 2019
Appl. No.:

16/548255
Inventors:

- Santa Clara CA, US
Kaizad MISTRY - Lake Oswego OR, US
Paul R. START - Chandler AZ, US
Nisha ANANTHAKRISHNAN - Chandler AZ, US
Yawei LIANG - Chandler AZ, US
Jigneshkumar P. PATEL - Chandler AZ, US
Sairam AGRAHARAM - Chandler AZ, US
Liwei WANG - Phoenix AZ, US
International Classification:

H01L 25/065
H01L 25/18
H01L 25/00
H01L 21/56
H01L 23/367
H01L 23/29
H01L 23/31
H01L 23/00
Abstract:

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.