Nikhil A Patil

US Patent:

20100250227, Sep 30, 2010

Filed:

Mar 30, 2010

Appl. No.:

12/749595

Inventors:

Derek Chiou - Austin TX, US
Hari Angepat - Austin TX, US
Nikhil Patil - Austin TX, US

Assignee:

Board of Regents The University of Texas System - Austin TX

International Classification:

G06G 7/62

US Classification:

703 21

Abstract:

A method, computer program product and system for detecting that a functional model execution is out-of-order with respect to a target execution. A value of a store instruction to be stored in a memory address, where the store instruction is executed by the functional model, is received by the timing model. This value is stored by the timing model in a target oracle memory at a time when the target system would execute the store instruction. The timing model compares the value in the target oracle memory with the value of a load instruction to be loaded from the same memory address, which is received from the functional model, at a time when the target system would execute the load instruction. The timing model detects an out-of-order instruction stream with respect to the target instruction stream if there is a miscomparison.

US Patent:

20170097824, Apr 6, 2017

Filed:

Jul 5, 2016

Appl. No.:

15/202351

Inventors:

- Shanghai, CN
NIKHIL A. PATIL - Austin TX, US

International Classification:

G06F 9/30
G06F 9/38

Abstract:

A microprocessor is configured for unchained and chained modes of split execution of a fused compound arithmetic operation. In both modes of split execution, a first execution unit executes only a first part of the fused compound arithmetic operation and produces an intermediate result thereof, and a second instruction execution unit receives the intermediate result and executes a second part of the fused compound arithmetic operation to produce a final result. In the unchained mode, execution is accomplished by dispatching separate split-execution microinstructions to the first and second instruction execution units. In the chained mode, execution is accomplished by dispatching a single split-execution microinstruction to the first instruction execution unit and sending a chaining control signal or signal group to the second execution unit, causing it to execute its part of the fused arithmetic operation without needing an instruction.

US Patent:

20170060581, Mar 2, 2017

Filed:

Aug 19, 2016

Appl. No.:

15/241765

Inventors:

- Shanghai, CN
NIKHIL A. PATIL - Austin TX, US

International Classification:

G06F 9/30
G06F 13/362
G06F 13/16

Abstract:

An arbiter that performs accelerated arbitration by approximating relative ages including a memory, blur logic, and grant logic. Multiple entries arbitrate for one or more resources. The memory stores age values each providing a relative age between each pair of entries, and further stores blurred age values. The entries are divided into subsets in which each entry belongs to only one subset. The blur logic determines each blurred age value to indicate a relative age between an entry of a first subset and an entry of a different subset for each pair of subsets. The grant logic grants access by an entry to a resource based on relative age using corresponding age values when comparing relative age between entries within a common subset, and using corresponding blurred age values when comparing relative age between entries in different subsets. Each blurred age value represents multiple age values to simplify arbitration.