Nathan P Chelstrom

US Patent:

7406640, Jul 29, 2008

Filed:

Mar 31, 2006

Appl. No.:

11/278313

Inventors:

Louis Bernard Bushard - Rochester MN, US
Nathan Paul Chelstrom - Cedar Park TX, US
Naoki Kiryu - Machida, JP
David John Krolak - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714726, 714733

Abstract:

A method and apparatus for loading a ring of non-scan latches for a logic built-in self-test. A logic built-in self-test value is loaded into a scannable latch from the logic built-in self-test. An override control signal is asserted in response to loading the logic built-in self-test value into the scannable latch. A non-scan latch is forced to load the logic built-in self-test value from the scannable latch in response to asserting the override control signal. Logic paths in the ring of non-scan latches are exercised. The non-scan latch is part of the logical paths. The test results are captured from the logic paths and the test results are compared against expected test results to determine if the logic paths within the ring of non-scan latches are functioning properly.

US Patent:

7478300, Jan 13, 2009

Filed:

Apr 28, 2006

Appl. No.:

11/380677

Inventors:

Nathan P. Chelstrom - Cedar Park TX, US
Steven R. Ferguson - Granite Shoals TX, US
Mack W. Riley - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714729, 714 30, 714718, 714724, 714719, 714726, 714727, 714728, 714732, 714734, 714736, 714738, 714739, 714742, 714744

Abstract:

A method for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device is provided. With the method, each clock domain has its own scan paths that do not cross domain boundaries. By eliminating the scanning across the boundaries, the requirement to have two clock grids in the asynchronously clocked domains may be eliminated. As a result, circuit area and design time with regard to the clock distribution design are reduced. In addition, removing the second clock grid, i. e. the high speed core or system clock, in the asynchronously clocked domains removes the requirement to have a multiplexing scheme for selection of clocking signals in the asynchronous domain. In addition to the above, the system and method provide boundary built-in-self-test logic for testing the functional crossing logic of boundaries between the clock domains in a functional mode of operation.

US Patent:

7484153, Jan 27, 2009

Filed:

Dec 6, 2005

Appl. No.:

11/295057

Inventors:

Naoki Kiryu - Tokyo, JP
Mack Wayne Riley - Austin TX, US
Nathan Paul Chelstrom - Austin TX, US

Assignee:

Kabushiki Kaisha Toshiba - Tokyo
International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714733, 714727

Abstract:

Systems and methods for performing logic built-in self-tests (LBISTs) in digital circuits, where boundary scan chains in functional blocks of the circuits can be selectively coupled/decoupled to isolate the functional blocks during LBIST testing. In one embodiment, processor cores of a multiprocessor chip are isolated and LBIST testing is performed to determine whether any of the processor cores is malfunctioning. If none of the processor cores malfunctions, the processor cores are tested in conjunction with the supporting functional blocks of the device to determine whether the multiprocessor is fully functional. If one or more processor cores malfunctions, these processor cores are isolated and the remaining processor cores are tested in conjunction with the supporting functional blocks of the device to determine whether the multiprocessor operates properly with reduced functionality.

US Patent:

7492793, Feb 17, 2009

Filed:

Oct 20, 2005

Appl. No.:

11/255156

Inventors:

Nathan P. Chelstrom - Cedar Park TX, US
Mack W. Riley - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04J 3/06

US Classification:

370503, 370535, 714731, 714744, 713400, 713600

Abstract:

A method for controlling asynchronous clock domains to perform synchronous operations is provided. With the method, when a synchronous operation is to be performed on a chip, the latches of the functional elements of the chip are controlled by a synchronous clock so that the latches are controlled synchronously even across asynchronous boundaries of the chip. The synchronous operation may then be performed and the chip's functional elements returned to being controlled by a local clock in an asynchronous manner after completion of the synchronous operation. This synchronous operation may be, for example, a power on reset (POR) operation, a manufacturing test sequence, debug operation, or the like.

US Patent:

7500164, Mar 3, 2009

Filed:

Jun 1, 2006

Appl. No.:

11/421515

Inventors:

Nathan P. Chelstrom - Cedar Park TX, US
Steven R. Ferguson - Granite Shoals TX, US
Mack W. Riley - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714729, 714724, 714 30, 714726, 714727, 714732

Abstract:

A method for testing an integrated circuit device with asynchronous clocks or dissimilar design methodologies is provided. With the method, each clock domain has its own scan paths that do not cross domain boundaries. By eliminating the scanning across the boundaries, the requirement to have two clock grids in the asynchronously clocked domains may be eliminated. As a result, circuit area and design time with regard to the clock distribution design are reduced. In addition, removing the second clock grid, i. e. the high speed core or system clock, in the asynchronously clocked domains removes the requirement to have a multiplexing scheme for selection of clocking signals in the asynchronous domain. In addition to the above, the method provides boundary built-in-self-test logic for testing the functional crossing logic of boundaries between the clock domains in a functional mode of operation.

US Patent:

7516350, Apr 7, 2009

Filed:

Sep 9, 2004

Appl. No.:

10/937689

Inventors:

Nathan Chelstrom - Cedar Park TX, US
Mack Wayne Riley - Austin TX, US
Michael Fan Wang - Austin TX, US
Stephen Douglas Weitzel - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/00
H03L 7/00

US Classification:

713500, 713501, 331 2

Abstract:

The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element.

US Patent:

7562272, Jul 14, 2009

Filed:

Oct 6, 2005

Appl. No.:

11/245308

Inventors:

Irene Beattie - Leander TX, US
Nathan P. Chelstrom - Cedar Park TX, US
Matthew E. Fernsler - Round Rock TX, US
Mack W. Riley - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714726, 714724, 375376, 702 79

Abstract:

An apparatus and method for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the apparatus and method, a portion of the eFuses present in the integrated circuit are reserved for the PLL configuration data. Upon power up, a power up controller and eFuse controller direct the sensing and serial transfer of the data in the portion of eFuses to the PLL under the reference clock. When the transfer is complete, the power up controller directs the PLL logic to load the configuration data and start. The mechanism of the present invention allows manufacturing to tailor the PLL configuration on a given device based on the characteristics of that device and its intended usage. Thus, the same PLL may be used in the same or different architectures to perform different operations based on the configuration data passed into the PLL from the eFuses.

US Patent:

7627771, Dec 1, 2009

Filed:

Oct 4, 2005

Appl. No.:

11/242674

Inventors:

Nathan P. Chelstrom - Cedar Park TX, US
Mack W. Riley - Austin TX, US
Shoji Sawamura - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/12
G06F 13/42
H04L 5/00
H04L 7/00

US Classification:

713400, 713324, 713500, 714 30, 714 34

Abstract:

A clock control hierarchy is provided that is comprised of synchronous and asynchronous hold request signals that are used to start and stop functional units of a chip. Pervasive logic is provided that uses a synchronous “chip hold” signal and asynchronous latch/functional unit hold signals to individually target functional units and latches that are to remain in a held state once the “chip hold” state is released. With the present invention, a chip hold request is first activated followed by scannable latch and non-scannable latch hold requests being activated to identify which latches will be clocked or not clocked when the chip hold is released. Functional unit hold signals are activated to place certain ones of the functional units of the chip in a hold state. The chip hold request is deactivated and the chip operates with the selected functional units and latches being maintained in a held state.