Nandor G Thoma
age ~82
from Palm Bay, FL
- Also known as:
-
- Nandor Gyorgy Thoma
- Nandor Cynthia Thoma
- Gyorgy Thoma Nandor
- Nador G Thoma
- Nandor G Thomas
- Thoma Nandor
- Thona Nandor
- Phone and address:
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1290 Emerson Dr NE, Melbourne, FL 32907
321-676-2865
Nandor Thoma Phones & Addresses
- 1290 Emerson Dr NE, Palm Bay, FL 32907 • 321-676-2865
- Melbourne, FL
- Idaho Falls, ID
- 7873 Flager Cir, Manassas, VA 20109 • 703-368-0363
- Vero Beach, FL
- Austin, TX
- Amelia, LA
- Plano, TX
- Boca Raton, FL
Us Patents
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Single-Event Upset Tolerant Latch For Sense Amplifiers
view source -
US Patent:6487134, Nov 26, 2002
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Filed:Aug 9, 2001
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Appl. No.:09/927059
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Inventors:Nandor G. Thoma - Manassas VA
Scott E. Doyle - Centreville VA -
Assignee:BAE Systems Information and Electronic Systems Integration, Inc. - Nashua NH
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International Classification:G11C 700
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US Classification:365205, 365207, 365208, 36518905, 327 51, 327 57
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Abstract:A single-event upset tolerant sense latch circuit for sense amplifiers is disclosed. The single-event upset tolerant sense latch circuit includes a first set of isolation transistors, a second set of isolation transistors, a first set of dual-path inverters, a second set of dual-path inverters, and an isolation transistor. The first set of isolation transistors is coupled to a first bitline, and the second set of isolation transistors is coupled to a second bitline. The second bitline is complementary to the first bitline. The first set of dual-path inverters is coupled to the first set of isolation transistors, and the first set of dual-path inverters includes a first transistor connected to a second transistor in series along with a third transistor connected to a fourth transistor in series. The second set of dual-path inverters is coupled to the second set of isolation transistors, and the second set of dual-path inverters includes a fifth transistor connected to a sixth transistor in series along with a seventh transistor connected to an eighth transistor in series. The isolation transistor couples the first and second sets of dual-path inverters to ground.
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Ring Oscillator Providing Single Event Transient Immunity
view source -
US Patent:6642802, Nov 4, 2003
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Filed:Dec 20, 2001
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Appl. No.:10/029716
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Inventors:Kenneth R. Knowles - Manassas VA
Nandor G. Thoma - Manassas VA -
Assignee:BAE Systems Information and Electronic Systems Integration, Inc. - Manassas VA
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International Classification:H03B 2700
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US Classification:331 57, 331177 R
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Abstract:A dual path ring oscillator core includes three dual path inverters, each having a first inverter and a second inverter. Within the first inverter, one transistor is coupled to a first output of a previous dual path inverter, while another transistor is coupled to a second output of the previous dual path inverter. Within the second inverter, one transistor is coupled to the second output of the previous dual path inverter, while another transistor is coupled to the previous dual path inverters first output. A first and a final dual path inverter are analogously coupled. A transient pulse will not propagate through successive dual path inverter stages. A dual to single path converter is coupled to receive signals output by the final dual path inverter. If a transient signal appears at a dual to single path converter input, stray output node capacitance maintains a correct output signal value.
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Single-Event Upset Tolerant Static Random Access Memory Cell
view source -
US Patent:20060133134, Jun 22, 2006
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Filed:Dec 16, 2004
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Appl. No.:11/014315
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Inventors:Scott Doyle - Centreville VA, US
Nandor Thoma - Vero Beach FL, US -
International Classification:G11C 11/00
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US Classification:365154000
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Abstract:A single-event upset tolerant random access memory cell is disclosed. The single-event upset tolerant memory cell includes a first and second sets of access transistors along with a first and second sets of dual-path inverters. The first set of access transistors is coupled to a first bitline, and the second set of access transistors is coupled to a second bitline that is complementary to the first bitline. The first set of dual-path inverters, which is coupled to the first set of access transistors, includes a first transistor connected to a second transistor in series and a third transistor connected to a fourth transistor in series. The second set of dual-path inverters, which is coupled to the second set of access transistors, includes a fifth transistor connected to a sixth transistor in series and a seventh transistor connected to an eighth transistor in series.
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Classmates
Nandor G Thoma
view sourceSchools:
Burr & Burton Academy Manchester VT 1956-1960
Burr & Burton Academy...
view sourceGraduates:
Nandor G Thoma (1956-1960),
Tammy Gellar (1987-1991),
Tammy Gaudette (1987-1991),
Gregory Porter (1966-1970),
Max Skapof (1986-1990),
Melissa Griffin (1992-1996)
Tammy Gellar (1987-1991),
Tammy Gaudette (1987-1991),
Gregory Porter (1966-1970),
Max Skapof (1986-1990),
Melissa Griffin (1992-1996)
Get Report for Nandor G Thoma from Palm Bay, FL, age ~82