Michael D Decesaris

US Patent:

20130272515, Oct 17, 2013

Filed:

Apr 11, 2012

Appl. No.:

13/444389

Inventors:

Michael DeCesaris - Carrboro NC, US
William M. Megarity - Roxboro NC, US
Luke D. Remis - Raleigh NC, US
Gregory D. Sellman - Morrisville NC, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H04M 3/42

US Classification:

37921002

Abstract:

Selectively filtering incoming communications events in a communications device, including: receiving, by a communications event filtering module, an incoming communications event; determining, by the communications event filtering module, whether the communications device is currently servicing a call; responsive to determining that the communications device is currently servicing a call, determining, by the communications event filtering module, whether the call is interruptible; and responsive to determining that the call is not interruptible, blocking, by the communications event filtering module, the incoming communications event from presentation by the communications device until the call has ended.

US Patent:

20130275636, Oct 17, 2013

Filed:

Apr 12, 2012

Appl. No.:

13/445235

Inventors:

MICHAEL DECESARIS - CARRBORO NC, US
LUKE D. REMIS - RALEIGH NC, US
GREGORY D. SELLMAN - MORRISVILLE NC, US
STEVEN L. VANDERLINDEN - CHAPEL HILL NC, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

G06F 13/42

US Classification:

710110

Abstract:

A hardware system comprises a master device and a slave device that are coupled by a signal line. A frequency generator in the master device places a selected frequency signal on the signal line. A frequency detector/comparator in the slave device, which is coupled to the signal line, determines whether the selected frequency signal on the signal line matches a predetermined frequency for the slave device. If the selected frequency signal matches the predetermined frequency, then a chip select node on the slave device is enabled, in order to permit a data exchange session between the master device and the slave device.

US Patent:

20130304954, Nov 14, 2013

Filed:

May 9, 2012

Appl. No.:

13/467332

Inventors:

MICHAEL DECESARIS - CARRBORO NC, US
STEVEN C. JACOBSON - MEBANE NC, US
LUKE D. REMIS - RALEIGH NC, US
GREGORY D. SELLMAN - MORRISVILLE NC, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

G06F 13/00

US Classification:

710110

Abstract:

Optimizing an IC bus frequency, the bus including signal lines coupling a master and slave nodes, a signal line coupled to a rise time detection circuit monitoring a voltage of the signal line, the voltage alternating between a logic low and logic high, where optimizing the frequency includes: detecting, during a rise in the signal line, a first voltage, the first voltage being greater than the logic low voltage; starting a counter to increment once for each clock period of the circuit; detecting a second voltage on the signal line, the second voltage greater than the first and less than the logic high; stopping the counter; calculating, in dependence upon the clock period and the counter value, a rise time; determining whether the rise time is greater than a maximum threshold; and increasing the IC bus frequency if the calculated rise time is greater than the maximum threshold.

US Patent:

20130343197, Dec 26, 2013

Filed:

Jun 22, 2012

Appl. No.:

13/530245

Inventors:

Michael DeCesaris - Carrboro NC, US
Steven C. Jacobson - Mebane NC, US
Luke D. Remis - Raleigh NC, US
Gregory D. Sellman - Morrisville NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/26

US Classification:

370241

Abstract:

Operating a demultiplexer on an IC bus, the demultiplexer including a set of input signal lines from an IC master and a plurality of sets of output signal lines, the demultiplexer configured to couple the inputs among the output in dependence upon a demultiplexer select signal line that couples the demultiplexer to a rise time detection circuit, where the rise time detection circuit is also coupled to the input signal lines and the rise time detection circuit: monitors a voltage of at least one of the input signal lines, including: receiving, from the IC master, a signal on one of the lines; and detecting rise time of the signal; and if the rise time of the signal is less than a predefined threshold, configuring the demultiplexer to vary the coupling of the input signal lines from a first set of outputs to a second set.

US Patent:

20130346658, Dec 26, 2013

Filed:

Jun 22, 2012

Appl. No.:

13/530284

Inventors:

Michael DeCesaris - Carrboro NC, US
Steven C. Jacobson - Mebane NC, US
Luke D. Remis - Raleigh NC, US
Gregory D. Sellman - Morrisville NC, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

G06F 13/40

US Classification:

710110

Abstract:

Chip select (‘CS’) multiplication in an SPI system that includes an SPI master, a CS multiplier, a plurality of SPI slaves, and a fall time detection circuit, where the SPI master is coupled to the CS multiplier and the fall time detection circuit by a CS signal line, the CS multiplier includes a plurality of CS outputs with each CS output coupled to an SPI slave, and CS multiplication includes: receiving, from the SPI master, the CS signal on the CS signal line; detecting fall time of the CS signal; and, if the fall time of the CS signal is less than a predefined threshold, configuring, by the fall-time detection circuit, the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output.

US Patent:

20130346763, Dec 26, 2013

Filed:

Jun 22, 2012

Appl. No.:

13/530473

Inventors:

MICHAEL DECESARIS - Carrboro NC, US
LUKE D. REMIS - Raleigh NC, US
GREGORY D. SELLMAN - Morrisville NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/26
G06F 1/04

US Classification:

713300

Abstract:

Increasing data transmission rate in an IC system that includes an IC source device and an destination device, the source device coupled to the destination device through an SDL and SCL, including: receiving in parallel, by the destination device, an SDL data signal and an SCL data signal, the SCL data signal encoded with bits; and, for each bit of the SCL data signal: detecting rise time of the bit and determining, in dependence upon the detected rise time, whether the bit represents a first binary value or a second binary value including: determining that the bit represents a first binary value when the detected rise time is less than a predefined threshold; and determining that the bit represents a second binary value when the detected rise time is not less than the predefined threshold.

US Patent:

20130346835, Dec 26, 2013

Filed:

Jun 22, 2012

Appl. No.:

13/530318

Inventors:

Michael DeCesaris - Carrboro NC, US
Steven C. Jacobson - Mebane NC, US
Luke D. Remis - Raleigh NC, US
Gregory D. Sellman - Morrisville NC, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

H03M 13/09
G06F 11/10

US Classification:

714800, 714E11032

Abstract:

Detecting data transmission errors in an IC system that includes a source device, an destination device, and a signal line coupling the IC source and destination device, including: receiving, by the IC destination device from the IC source device, a data transmission signal, the data transmission signal encoded with a set of bits; detecting, by the IC destination device, rise time of a preselected bit in the set of bits; if the detected rise time is less than a predefined threshold, determining that the IC source device injected a parity bit in the signal, and if the detected rise time is not less than the predefined threshold, determining that the IC source device did not inject a parity bit in the signal; and determining whether the data transmission signal includes an error in dependence upon the parity of the set of bits.

US Patent:

20140013017, Jan 9, 2014

Filed:

Jul 4, 2012

Appl. No.:

13/541749

Inventors:

Michael DeCesaris - Carrboro NC, US
Pravin S. Patel - Cary NC, US
Luke D. Remis - Raleigh NC, US
Gregory D. Sellman - Morrisville NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/42

US Classification:

710105

Abstract:

A method, device and computer program product for providing multi-protocol communication on an inter-integrated circuit (I2C) bus. The method for providing multi-protocol communication on an inter-integrated circuit (I2C) bus can include issuing a start command by a bus management device onto the I2C bus. Thereafter, the bus management device can send an embedded differential protocol to a non-I2C device. Once communication with the non-I2C device is completed, the bus management device can issue a stop command to release the I2C bus. In one aspect of this embodiment, the method can include receiving a response from the non-I2C device.