Michael J Coln

US Patent:

7136005, Nov 14, 2006

Filed:

May 5, 2005

Appl. No.:

11/122587

Inventors:

Colin G. Lyden - Baltimore Co. Cork, IE
Michael C. Coln - Lexington MA, US
Robert Brewer - Lambourn, GB

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 1/50

US Classification:

341166, 341155

Abstract:

An accurate, low noise conditionally resetting integrator circuit in an analog to digital system samples, with an analog to digital converter, the output of an integrating circuit a number of times during a measuring period; isolates the input for the integrating circuit during sample event; generates a reset signal in response to the integrating circuit output reaching a predetermined level; and resets the feedback capacitor of the integrating circuit by isolating it from the amplifier circuit of the integrating circuit and connecting it to a reference source during a sample event.

US Patent:

7737409, Jun 15, 2010

Filed:

Jun 12, 2008

Appl. No.:

12/138078

Inventors:

Shrenik A. Deliwala - Andover MA, US
Michael C Coln - Lexington MA, US
Alain Valentin Guery - Andover MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G01T 1/24

US Classification:

25037001

Abstract:

Described is a die having photodetectors provided on a first surface thereof. The die includes an insulative shell member, a conductive shell member and a photodetector conductor. The insulative shell member extends around a periphery of the photodetector receptors and extending through a depth of the semiconductor die. The conductive shell member bridges the insulative shell member and extends through the depth of the semiconductor die. The photodetector conductors are provided on the first surface of the semiconductor die and electrically couple respective photodetectors with a corresponding conductive shell member. Also described is a process for making a semiconductor die and an integrated circuit structure.

US Patent:

8203357, Jun 19, 2012

Filed:

Dec 4, 2009

Appl. No.:

12/630999

Inventors:

Yoshinori Kusuda - Woburn MA, US
Michael Coln - Lexington MA, US
Gary Carreau - Plaistow NH, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03K 17/16
H03K 19/003

US Classification:

326 21, 326 22, 326 26, 326 93

Abstract:

An integrated circuit may include a plurality of circuit sub-systems that include at least one converter circuit operating in respective critical phases and non-critical phases of operation, a clock distribution circuit that has an input for an externally-supplied clock signal that is active during the non-critical phases and inactive during the critical phases, and a clock generator to generate an internal clock signal to the converter circuit that is active when the external-supplied clock signal is inactive.

US Patent:

8228217, Jul 24, 2012

Filed:

Jul 29, 2010

Appl. No.:

12/846649

Inventors:

Lalinda Fernando - Burlington MA, US
Michael Coln - Lexington MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 1/48

US Classification:

341116, 341112, 341155

Abstract:

A system and method for reducing noise in resolver-to-digital converters (RDC) using a cascaded tracking loop filter. In some embodiments, one or more tracking loop filters may be implemented in a cascade to attenuate carrier harmonic frequencies in the digitized output of an RDC. Where a plurality of tracking loop filters are implemented, the output of one tracking loop filter may be input into a successive tracking loop filter.

US Patent:

8441104, May 14, 2013

Filed:

Nov 16, 2011

Appl. No.:

13/297571

Inventors:

Lejun Hu - Somerville MA, US
Srivatsan Parthasarathy - Burlington MA, US
Michael Coln - Lexington MA, US
Javier Salcedo - North Billerica MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H01L 27/02

US Classification:

257546, 257355, 257443, 257173, 257328, 257E29015, 257E23194, 257E21361

Abstract:

A semiconductor device formed on a substrate includes a first diode junction formation, a second diode junction formation, and at least one through-silicon-via (TSV), in which a cathode and an anode of the first diode are cross-connected to an anode and cathode of the second diode through the at least one TSV for achieving electrical robustness in through-silicon-via based integrated circuits, including photosensitive devices and circuits for signal processing applications.

US Patent:

8514014, Aug 20, 2013

Filed:

Feb 9, 2011

Appl. No.:

13/023751

Inventors:

Cathal Murphy - Annacotty, IE
Michael Coln - Lexington MA, US
Gary Carreau - Plaistow NH, US
Alain Valentin Guery - Andover MA, US
Bruce Amazeen - Ipswich MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03F 1/02

US Classification:

330 9, 341172

Abstract:

An amplifier system can include a feedback amplifier circuit having an amplifier, a feedback capacitor connected between an input terminal and an output terminal of the amplifier by at least one first switch, and a reset capacitor connected across the feedback capacitor by at least one second switch and between a pair of reference voltages by at least one third switch. During an input-signal processing phase of operation, a control circuit may close the at least one first switch and open the at least one second switch to electrically connect the feedback capacitor between the input and output terminals to engage feedback processing by the feedback amplifier circuit, and close the third switch to electrically connect the reset capacitor between the first and second voltages to charge the reset capacitor to a selectable voltage difference. During a reset phase of operation, the control circuit may open the at least one third switch, close the at least one second switch and open the at least one first switch to electrically connect the reset capacitor across the feedback capacitor to reset the feedback capacitor using the reset capacitor. The amplifier system can optionally include a plurality of the feedback amplifier circuits.

US Patent:

8514112, Aug 20, 2013

Filed:

Jun 24, 2011

Appl. No.:

13/168017

Inventors:

Roderick McLachlan - Edinburgh, GB
Michael Coln - Lexington MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 1/06

US Classification:

341118

Abstract:

The invention provides a systematic error correction network coupled to a converter. The converter may display a systematic non-linearity error, and the systematic error correction network shapes a correction transform function that acts like counter distortion function for the non-linearity error. The systematic error correction network then scales the correction transform function according to a reference variable, where the magnitude of non-linearity error is related to the reference variable. The scaled correction transform function is then applied to the converter path in order to generate a corrected analog output signal.

US Patent:

8525299, Sep 3, 2013

Filed:

Mar 6, 2013

Appl. No.:

13/786646

Inventors:

Lejun Hu - Somerville MA, US
Srivatsan Parthasarathy - Burlington MA, US
Michael Coln - Lexington MA, US
Javier Salcedo - North Billerica MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H01L 27/02

US Classification:

257546, 257173, 257328, 257355

Abstract:

A semiconductor device formed on a substrate includes a first diode junction formation, a second diode junction formation, and at least one through-silicon-via (TSV), in which a cathode and an anode of the first diode are cross-connected to an anode and cathode of the second diode through the at least one TSV for achieving electrical robustness in through-silicon-via based integrated circuits, including photosensitive devices and circuits for signal processing applications.